Heterogeneous integration of integrated circuit device and companion device

Patent metadata

Field	Value
Publication number	US-9865567-B1
Application number	US-201715423303-A
Country	US
Kind code	B1
Filing date	Feb 2, 2017
Priority date	Feb 2, 2017
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor assembly, comprising:
forming first integrated circuit (IC) dies and dummy dies;
forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies;
attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites;
processing a backside and the top side of the interposer wafer;
removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and
attaching the second IC dies to the interposer wafer at the exposed second mounting sites.

2. The method of claim 1 , further comprising:
dicing the interposer wafer into a plurality of semiconductor devices each having a first IC die and a second IC die; and
attaching each semiconductor device to a package substrate.

3. The method of claim 2 , further comprising:
attaching a lid to each package substrate to cover each semiconductor device attached thereto.

4. The method of claim 1 , further comprising:
depositing underfill beneath each of the second IC dies after the second IC dies are attached to the exposed second mounting sites of the interposer wafer.

5. The method of claim 1 , wherein the step of attaching the dummy dies to the interposer wafer comprises:
depositing adhesive over each of the second mounting sites and placing the dummy dies on the adhesive.

6. The method of claim 5 , wherein the dummy dies comprises glass substrates, and wherein the step of removing the dummy dies comprises:
removing the dummy dies using a thermal, chemical, mechanical, or optical process; and
cleaning the adhesive from the second mounting sites of the interposer wafer.

7. The method of claim 1 , further comprising:
molding the first IC dies and the dummy dies on the top side of the interposer wafer prior to processing the backside and the top side of the interposer wafer.

8. The method of claim 7 , wherein the step of processing the top side of the interposer wafer comprises grinding the top side of the interposer wafer to reveal to surfaces of the first IC dies and the dummy dies.

9. The method of claim 1 , wherein the step of processing the backside of the interposer wafer comprises:
performing at least one of deposition, polishing, and etching of the backside of the interposer wafer; and
bumping the backside of the interposer wafer.

10. The method of claim 9 , further comprising:
performing electrical testing of the interposer wafer after the bumping of the backside of the interposer wafer.

11. The method of claim 1 , wherein the dummy dies comprise semiconductor substrates, and wherein the step of attaching the dummy dies to the interposer substrate comprises soldering the dummy dies to the second mounting sites.

12. The method of claim 11 , further comprising:
performing electrical probing of the interposer wafer after the processing of the backside of the interposer wafer.

13. The method of claim 1 , wherein a thickness of each of the dummy dies and a thickness of each of the first IC dies is substantially the same.

14. The method of claim 12 , wherein a thickness of each of the second IC dies is different than each of the first IC dies.

15. The method of claim 1 , wherein the second IC dies each include pre-applied underfill material, and wherein the step of attaching the second IC dies comprises bonding the second IC dies to the interposer wafer using thermal compression bonding.

16. The method of claim 1 , wherein the first IC dies are programmable IC dies and the second IC dies are memory dies.

Assignees

• Xilinx Inc

Inventors

• Chaware Raghunandan
• Hariharan Ganesh
• Singh Inderjit
• Majumdar Amitava
• O'Rourke Glenn

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title