Package-on-package assembly and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9437583-B1
Application number	US-201615134396-A
Country	US
Kind code	B1
Filing date	Apr 21, 2016
Priority date	Jun 9, 2015
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an interposer having a first side and a second side, an active chip mounted on the first side within a chip mounting area through first bumps, and a dummy chip mounted on the first side within a peripheral area. The dummy chip is directly mounted on a passivation layer of the interposer. A dielectric layer covers the active chip and the dummy chip. At least one TSV connecter penetrates through the dielectric layer and the dummy chip. A molding compound is disposed on the first side. The molding compound covers the active chip and the TSV chip. Solder bumps are mounted on the second side.

First claim

What is claimed is:

1. A package-on-package (PoP) assembly, comprising:
a bottom die package comprising
an interposer having a first side and a second side opposite to the first side;
at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps;
at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the dummy chip is directly mounted on a passivation layer of the interposer;
a dielectric layer covering the at least one active chip and the at least one dummy chip;
at least one TSV connecter penetrating through the dielectric layer and the dummy chip;
a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and
a plurality of solder bumps mounted on the second side;

a top die package mounted on the bottom die package.

2. The PoP assembly according to claim 1 , wherein the dummy chip is directly mounted on the passivation layer by using an adhesive.

3. The PoP assembly according to claim 1 , wherein TSV connecter is electrically connected to a metal trace pattern on the dielectric layer.

4. The PoP assembly according to claim 3 , wherein the top die package is mounted on the bottom die package through a plurality of second bumps disposed on the metal trace pattern.

Assignees

• Inotera Memories Inc

Inventors

• Shih Shing-Yih
• Shih Neng-Tai

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title