Method of forming trench semiconductor device having multiple trench depths

Patent metadata

Field	Value
Publication number	US-9859449-B2
Application number	US-201715627281-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Mar 6, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
providing a region of semiconductor material having a first conductivity type and a major surface;
forming a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein:
at least a portion of the termination trench extends to a first depth; and
the termination trench has a first width;

forming an active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein:
the active trench has a second width less than the first width;
the first depth is greater than the second depth;
a portion of the region of semiconductor material is laterally interposed between the active trench and the termination trench in a cross-sectional view; and
the portion of the region of semiconductor material is devoid of trench structures whereby the active trench is a closest trench structure to the termination trench in the cross-sectional view;

forming a first conductive material having a first portion within the active trench and separated from the region of semiconductor material by a first dielectric region and a second portion within the termination trench separated from the region of semiconductor material by a second dielectric region; and
forming a second conductive material adjoining a third portion of the major surface, wherein the second conductive material is configured to provide a Schottky barrier.

2. The method of claim 1 , wherein forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 3.0 microns.

3. The method of claim 1 , wherein forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 2.0 microns.

4. The method of claim 1 , wherein providing the region of semiconductor material comprises providing the region of semiconductor material comprising SiC.

5. The method of claim 1 , wherein forming the termination trench and forming the active trench comprises providing a second width to first width ratio in a range from approximately 0.005 to approximately 0.125.

6. The method of claim 1 , wherein forming the termination trench and forming the active trench comprises providing a second width to first width ratio that is less than or equal to approximately 0.03.

7. The method of claim 1 , wherein:
providing the region of semiconductor comprises providing a semiconductor layer adjoining a semiconductor substrate such that the semiconductor layer defines the major surface;
providing the semiconductor layer comprises providing the semiconductor layer having a first dopant concentration; and
providing the semiconductor substrate comprising providing the semiconductor substrate having a second dopant concentration greater than the first dopant concentration.

8. The method of claim 7 , wherein:
providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 1.5 microns to approximately 2.5 microns;
providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.0×10 16 atoms/cm 3 and approximately 1.0×10 17 atoms/cm 3 ; and
forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 2.0 microns.

9. The method of claim 7 , wherein:
providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 2.25 microns to approximately 3.25 microns;
providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.5×10 16 atoms/cm 3 and approximately 8.0×10 16 atoms/cm 3 ; and
forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 1.8 microns.

10. The method of claim 7 , wherein:
providing the semiconductor layer comprises providing the semiconductor layer having a thickness of approximately 2.7 microns to approximately 4.5 microns;
providing the first dopant concentration comprises providing the first dopant concentration in a range from approximately 1.0×10 16 atoms/cm 3 and approximately 6.0×10 16 atoms/cm 3 ; and
forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth in a range greater than zero to approximately 1.5 microns.

11. The method of claim 7 , wherein providing the semiconductor layer comprises providing the semiconductor layer having a non-uniform dopant profile.

12. The method of claim 7 , wherein:
forming the termination trench and forming the active trench comprises providing the first depth greater than the second depth to define a trench depth difference; and
providing the semiconductor layer comprises providing the first dopant concentration of approximately 6.0×10 16 atoms/cm 3 such that breakdown voltage of the semiconductor device is substantially constant over a range of trench depth difference between approximately 0.1 microns and approximately 1.0 microns.

13. The method of claim 1 further comprising providing a doped layer adjoining the third portion of the major surface adjacent to the second conductive material.

14. The method of claim 1 further comprising providing a doped region of a second conductivity type adjoining a side surface of the active trench.

15. The method of claim 1 further comprising forming a conductive layer electrically coupling the second conductive material to the first portion and the second portion of the first conductive material.

16. A method of forming a semiconductor device comprising:
providing a region of semiconductor material comprising a semiconductor layer adjoining a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration;
in a single step:
forming a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein the first trench extends to a first depth, and wherein the termination trench has a first width; and
forming a plurality of active trenches each extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein each active trench has a second width less than the first width, and wherein the first depth is greater than the second depth to define a trench depth difference, and wherein one of the active trenches is disposed in the region of semiconductor material as a closest trench structure to the termination trench;

forming a first conductive material within each active trench and separated from the region of semiconductor material by a dielectric region; and
forming a second conductive material having a first portion adjoining a third portion of the major surface, wherein the first portion of the second conductive material is configured to provide a Schottky barrier.

17. The method of claim 16 , wherein:
forming the second conductive material comprises:
providing the second conductive material having a second portion adjoining the f

Assignees

• Semiconductor Components Ind Llc

Inventors

• Quddus Mohammed Tanvir
• Mudholkar Mihir
• Thomason Michael

Classifications

• H10D8/051

  of Schottky diodes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/36

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic