Local germanium condensation for suspended nanowire and finFET devices

Patent metadata

Field	Value
Publication number	US-9859430-B2
Application number	US-201514755029-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.

First claim

What is claimed is:

1. A method of forming a suspended nanowire, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor layer and a hard mask layer formed on the semiconductor layer;
forming at least one fin in the semiconductor layer and the hard mask layer;
forming one or more spacers on one or more exposed sidewalls of the at least one fin;
etching exposed regions of the semiconductor layer;
subsequent to etching the exposed regions of the semiconductor layer, epitaxially forming a silicon-germanium layer on exposed portions of the semiconductor layer;
performing a thermal annealing process such that:
an annealed silicon-germanium region is formed within the semiconductor layer adjacent to the silicon-germanium layer; and
the annealed silicon-germanium region is a layer between the at least one fin and the semiconductor layer;

removing the annealed silicon-germanium region and the silicon-germanium layer; and
removing the hard mask layer and the spacer.

2. The method of claim 1 , wherein forming the at least one fin in the semiconductor layer and the hard mask layer comprises removing at least a portion of the hard mask layer and the semiconductor layer.

3. The method of claim 1 , wherein etching the exposed regions of the semiconductor layer comprises performing an isotropic etch process on the exposed regions of the semiconductor layer.

4. The method of claim 1 , wherein the thermal annealing process is performed in an inert environment.

5. The method of claim 1 , wherein the thermal annealing process is performed in an oxidizing environment.

6. The method of claim 1 , wherein the silicon-germanium region and the silicon-germanium layer are removed using a chemical vapor etch, wherein the chemical vapor used in the chemical vapor etch comprises hydrogen chloride.

7. The method of claim 1 , wherein the silicon-germanium region and the silicon-germanium layer are removed using a standard clean process, wherein the standard clean process utilizes ammonium hydroxide and hydrogen peroxide as etchants.

8. The method of claim 1 , wherein the silicon-germanium region comprises at least 15 percent germanium.

9. The method of claim 1 , wherein the hard mask layer comprises silicon oxide.

10. The method of claim 1 , wherein removing the annealed silicon-germanium region and the silicon germanium layer creates a gap between the at least one fin and the semiconductor layer.

Assignees

• IBM

Inventors

• Chang Josephine B
• Chang Leland
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title