FORMING SELF-ALIGNED NiSi PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD

Patent metadata

Field	Value
Publication number	US-2016163702-A1
Application number	US-201414560049-A
Country	US
Kind code	A1
Filing date	Dec 4, 2014
Priority date	Dec 4, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions

First claim

1 . A method comprising:
forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming embedded silicon germanium (eSiGe) source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an interlayer dielectric (ILD) over and between the first and second dummy gates; replacing the first and second dummy gates with first and second high-k/metal gates (HKMG), respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

2 . The method according to claim 1 , further comprising forming second spacers at opposite sides of each of the first and second dummy gates prior to forming the silicon cap.

3 . The method according to claim 2 , comprising forming the second spacers to a width of 1 to 20 nanometers (nm).

4 . The method according to claim 1 , comprising forming the silicon caps by epitaxially growing silicon on the eSiGe and raised source/drain regions concurrently.

5 . The method according to claim 1 , comprising forming the contact trench by reactive ion etching (RIE).

6 . The method according to claim 1 , comprising forming the silicide from nickel and the silicon cap.

7 . The method according to claim 1 , wherein the first metal gate and eSiGe source/drain regions form a P-type field effect transistor (PFET), and the second metal gate and raised source/drain regions form an N-type field effect transistor (NFET).

8 . A method comprising:
forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming embedded silicon germanium (eSiGe) source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming an interlayer dielectric (ILD) over and between the first and second dummy gates; replacing the first and second dummy gates with first and second high-k/metal gates (HKMG), respectively; forming a contact trench through the ILD into each of the eSiGe and raised source/drain regions; forming a silicon cap on each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

9 . The method according to claim 8 , comprising forming the silicon caps by epitaxially growing silicon on the eSiGe and raised source/drain regions concurrently.

10 . The method according to claim 8 , comprising forming the contact trench by reactive ion etching (RIE).

11 . The method according to claim 8 , comprising forming the silicide from nickel and the silicon cap.

12 . The method according to claim 8 , wherein the first metal gate and eSiGe source/drain regions form a P-type field effect transistor (PFET), and the second metal gate and raised source/drain regions form an N-type field effect transistor (NFET).

13 . A device comprising:
first and second high-k/metal gates (HKMG), each with spacers at opposite sides thereof, on a substrate; embedded silicon germanium (eSiGe) source/drain regions at opposite sides of the first HKMG; raised source/drain regions at opposite sides of the second HKMG; a silicon cap on each of the eSiGe and raised source/drain regions; an interlayer dielectric (ILD) over and between the first and second HKMGs; a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and a trench silicide over the eSiGe and raised source/drain regions.

14 . The device according to claim 13 , further comprising second spacers on the eSiGe and raised source/drain regions, between the first spacers and the silicon caps.

15 . The device according to claim 14 , wherein the second spacers have a width of 1 to 20 nanometers (nm).

16 . The device according to claim 13 , wherein the silicon caps are formed of silicon epitaxially grown to a thickness of 1 to 20 nm.

17 . The device according to claim 13 , wherein the trench silicide comprises nickel silicide (NiSi), formed with the silicon of the silicon caps.

18 . The device according to claim 13 , wherein the first metal gate and the eSiGe source/drain regions form a P-type field effect transistor (PFET), and the second metal gate and raised source/drain regions form an N-type field effect transistor (NFET).

19 . The device according to claim 13 , further comprising shallow trench isolation (STI) regions between the eSiGe and raised source/drain regions.

20 . (canceled)

Assignees

• Globalfoundries Inc

Inventors

• Wu Xusheng
• Hu Yue
• Wang Xin
• Lee Yong Meng
• Peng Wen-Pin
• Zhao Lun
• Tong wei-hua

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title