Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit

Patent metadata

Field	Value
Publication number	US-9859418-B2
Application number	US-201615234520-A
Country	US
Kind code	B2
Filing date	Aug 11, 2016
Priority date	Aug 14, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a first main surface; and
a transistor cell in the semiconductor substrate, the transistor cell comprising:
a source region;
a source contact electrically connected to the source region, the source contact comprising a first source contact portion and a second source contact portion;
a drain region;
a drain contact electrically connected to the drain region, the drain contact being disposed in a drain contact groove;
a body region; and
a gate electrode in a gate trench in the first main surface adjacent to the body region, the gate electrode being configured to control a conductivity of a channel in the body region, a longitudinal axis of the gate trench extending in a first direction parallel to the first main surface,

wherein the source region, the body region and the drain region being disposed along the first direction,
the second source contact portion being disposed at a second main surface of the semiconductor substrate,
the first source contact portion comprising a source conductive material in direct contact with the source region and that extends partially into a first doped portion of the semiconductor substrate, wherein the first doped portion includes a region arranged between the source conductive material and the second source contact portion,
the semiconductor substrate comprises the first doped portion and a second doped portion having a same conductivity type, the first doped portion having a larger distance to the first main surface than the second doped portion, the first doped portion having a larger doping concentration than the second doped portion, the first doped portion being a component of the first source contact portion, and
the drain contact groove at least partially extending into the second doped portion of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein the source conductive material extends in the semiconductor substrate to a depth larger than a depth of the gate trench.

3. The semiconductor device according to claim 1 , wherein the source conductive material is disposed in a source contact groove formed in the first main surface.

4. The semiconductor device according to claim 3 , wherein the source region is formed at a sidewall of the source contact groove.

5. The semiconductor device according to claim 3 , further comprising a body contact portion at a sidewall of the source contact groove, adjacent to the source region.

6. The semiconductor device according to claim 1 , further comprising a field plate in a field plate trench in the first main surface and a drain contact electrically connected to the drain region, the drain contact being disposed in a drain contact groove, the drain contact groove extending to a deeper depth than the field plate trench.

7. The semiconductor device according to claim 1 , wherein the first doped portion comprises a contact portion having a higher doping concentration than a remaining part of the first doped portion, the contact portion being in contact with the source conductive material.

8. The semiconductor device according to claim 1 , wherein the first doped portion and the second doped portion of the semiconductor substrate are of a first conductivity type, and the source region and the drain region are of a second conductivity type.

9. The semiconductor device according to claim 8 , wherein a pn junction is formed between the drain region and the second doped portion of the semiconductor substrate.

10. The semiconductor device according to claim 1 , further comprising a drain contact layer at the first main surface of the semiconductor substrate.

11. The semiconductor device according to claim 1 , further comprising a drift zone disposed between the body region and the drain region.

12. The semiconductor device according to claim 7 , wherein the remaining part of the first doped portion is arranged between the contact portion and the second source contact portion.

13. The semiconductor device according to claim 7 , wherein the contact portion is in contact with an end portion of the source conductive material and is arranged between the source conductive material and the remaining part of the first doped portion.

14. The semiconductor device according to claim 7 , wherein the remaining part of the first doped portion surrounds a portion of each of the source conductive material and the contact portion.

15. The semiconductor device according to claim 7 , wherein:
the first doped portion is arranged adjacent to and between each of the second doped portion and the second source contact portion.

16. An integrated circuit comprising:
a plurality of semiconductor devices, each of the plurality of semiconductor devices comprising:
a semiconductor substrate having a first main surface; and
a transistor cell in the semiconductor substrate, the transistor cell comprising:
a source region;
a source contact electrically connected to the source region, the source contact comprising a first source contact portion and a second source contact portion;
a drain region;
a drain contact electrically connected to the drain region, the drain contact being disposed in a drain contact groove;
a body region; and
a gate electrode in a gate trench in the first main surface adjacent to the body region, the gate electrode being configured to control a conductivity of a channel in the body region, a longitudinal axis of the gate trench extending in a first direction parallel to the first main surface,

wherein the source region, the body region and the drain region being disposed along the first direction,
the second source contact portion being disposed at a second main surface of the semiconductor substrate,
the first source contact portion comprising a source conductive material in direct contact with the source region and that extends partially into a first doped portion of the semiconductor substrate, wherein the first doped portion includes a region arranged between the source conductive material and the second source contact portion,
the semiconductor substrate comprises the first doped portion and a second doped portion having a same conductivity type, the first doped portion having a larger distance to the first main surface than the second doped portion, the first doped portion having a larger doping concentration than the second doped portion, the first doped portion being a component of the first source contact portion,
the drain contact groove at least partially extending into the second doped portion of the semiconductor substrate, and
the source regions of the plurality of semiconductor devices are electrically connected with a common terminal.

17. The integrated circuit according to claim 16 , wherein two adjacent ones of the transistor cells are arranged so as to share a common drain contact,
wherein the source contacts of the two adjacent ones of the transistor cells are disposed at opposing sides of the two adjacent ones of the transistor cells.

18. The integrated circuit according to claim 16 , wherein the drain regions of the plurality of semiconductor devices are electrically connected to one of a plurality of loads electrically, respectively.

19. The integrated circuit according to claim 18 , wherein the plurality of loads are connected parallel to corresponding ones of the plurality of semiconductor devices.

20. The integrated circuit according to claim 16 , wherein the drain region

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Meiser Andreas
• Gebhardt Karl-Heinz
• Schloesser Till
• Weber Detlef

Classifications

• H10P32/1204

  from a plasma phase · CPC title

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title