Semiconductor device, integrated circuit and method of forming a semiconductor device

Patent metadata

Field	Value
Publication number	US-9735243-B2
Application number	US-201314082491-A
Country	US
Kind code	B2
Filing date	Nov 18, 2013
Priority date	Nov 18, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

First claim

What is claimed is:

1. A semiconductor device comprising a transistor in a semiconductor body having a first main surface, the transistor comprising:
a source region;
a drain region;
a channel region;
a drift zone;
a source contact electrically connected to the source region;
a drain contact electrically connected to the drain region;
a gate electrode at the channel region, the channel region and the drift zone being disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region patterned into a first ridge by adjacent gate trenches in the semiconductor substrate, the adjacent gate trenches being spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the first ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction, respectively,
one of the source contact and the drain contact being adjacent to the first main surface, the other one of the source contact and the drain contact being adjacent to a second main surface that is opposite to the first main surface.

2. The semiconductor device according to claim 1 , further comprising a back side metallization over the second main surface, the back side metallization being connected to the source contact or the drain contact being adjacent to the second main surface.

3. The semiconductor device according to claim 2 , further comprising a sense contact at the first main surface, the sense contact being connected with the back side metallization via a back side contact.

4. The semiconductor device according to claim 3 , wherein the back side contact is disposed in a back side contact opening extending from the first to the second main surface.

5. The semiconductor device according to claim 1 , wherein the source and the drain region are disposed adjacent to the first main surface.

6. The semiconductor device according to claim 1 , wherein portions of the gate electrode are disposed in the gate trenches.

7. The semiconductor device according to claim 1 , further comprising field plate trenches disposed in the first main surface and extending in the first direction, portions of a field plate being disposed in the field plate trenches.

8. The semiconductor device according to claim 1 , further comprising an insulating layer in contact with the second main surface.

9. The semiconductor device according to claim 8 , further comprising a further semiconductor layer in contact with a back side of the insulating layer.

10. The semiconductor device according to claim 1 , wherein the one of the source contact and the drain contact adjacent to the second main surface is disposed in direct contact with a bottom side of the source region and is absent from the first main surface.

11. An integrated circuit comprising first and second transistors in a semiconductor body having a first main surface, respectively, each of the first and the second transistors comprising:
a source region;
a drain region;
a channel region;
a drift zone;
a source contact electrically connected to the source region;
a drain contact electrically connected to the drain region;
a gate electrode at the channel region, the channel region and the drift zone being disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface, the channel region patterned into a first ridge by adjacent gate trenches in the semiconductor substrate, the adjacent gate trenches being spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the first ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction, respectively,
one of the source contact and the drain contact of the first transistor being adjacent to the first main surface, the other one of the source contact and the drain contact of the first transistor being adjacent to a second main surface that is opposite to the first main surface.

12. The integrated circuit according to claim 11 , wherein the source contact of the first transistor and the drain contact of the second transistor are adjacent to one of the first and the second main surfaces and the drain contact of the first transistor and the source contact of the second transistor are adjacent to the other one of the first and second main surfaces.

13. The integrated circuit according to claim 12 , further comprising a metallization layer electrically connecting the source contact of the first transistor and the drain contact of the second transistor.

14. The integrated circuit according to claim 12 , further comprising an isolation trench insulating the first transistor from the second transistor, the isolation trench being disposed between the first and the second transistor.

15. The integrated circuit according to claim 11 , wherein the source contacts of the first and the second transistors are adjacent to one of the first and the second main surfaces and the drain contacts of the first and the second transistors are adjacent to the other one of the first and the second main surfaces.

16. The integrated circuit according to claim 11 , wherein the one of the source contact and the drain contact adjacent to the second main surface is disposed in direct contact with a bottom side of the source region or the drain region and is absent from the first main surface.

Assignees

• Infineon Technologies Ag

Inventors

• Meiser Andreas
• Weis Rolf
• Hirler Franz
• Vielemeyer Martin
• Zundel Markus
• Irsigler Peter

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H01L29/7835

  Electricity · mapped topic

• H01L29/66681

  Electricity · mapped topic