Method for forming semiconductor structure with metallic layer over source/drain structure
US-9324820-B1 · Apr 26, 2016 · US
Multiple step thin film deposition method for high conformality
US9859403B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9859403-B1 |
| Application number | US-201615174147-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jul 22, 2016 |
| Priority date | Jul 22, 2016 |
| Publication date | Jan 2, 2018 |
| Grant date | Jan 2, 2018 |
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Abstract
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During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.
First claim
Opening claim text (preview).
What is claimed as new is: 1. A method of forming a semiconductor structure comprising: forming a plurality of semiconductor fins on a substrate; forming a plurality of raised active regions on the semiconductor fins; forming a plasma within a vacuum chamber; depositing a first portion of a conformal conductive layer over the raised active regions at a first ion energy; and depositing a second portion of the conformal conductive layer over the first portion at a second ion energy. 2. The method of claim 1 , wherein the first ion energy is less than the second ion energy. 3. The method of claim 2 , wherein the conformal conductive layer does not merge adjacent raised active regions. 4. The method of claim 2 , wherein a self-bias voltage during deposition of the first portion is from 100 to 200 V. 5. The method of claim 2 , wherein a self-bias voltage during deposition of the second portion is from −50 to 90 V. 6. The method of claim 1 , wherein the first ion energy is greater than the second ion energy. 7. The method of claim 6 , wherein the conformal conductive layer merges adjacent raised active regions. 8. The method of claim 6 , wherein a self-bias voltage during deposition of the first portion is from −50 to 90 V. 9. The method of claim 6 , wherein a self-bias voltage during deposition of the second portion is from 100 to 200 V. 10. The method of claim 1 , wherein the first portion and the second portion each comprise titanium. 11. The method of claim 1 , wherein the vacuum chamber pressure is constant during deposition of the conformal conductive layer. 12. The method of claim 1 , wherein the power applied to the plasma is constant during deposition of the conformal conductive layer. 13. The method of claim 1 , wherein the oxygen concentration within the deposited layer is less than 500 ppm. 14. The method of claim 1 , wherein the halide concentration within the deposited layer is less than 500 ppm. 15. A method of forming a semiconductor structure within a vacuum chamber comprising: plasma depositing a first portion of a conformal conductive layer over raised regions disposed on a semiconductor substrate at a first ion energy; and plasma depositing a second portion of the conformal conductive layer over the first portion at a second ion energy. 16. The method of claim 15 , wherein a self-bias voltage during deposition of the first portion is from −50 to 90 V and a self-bias voltage during deposition of the second portion is from 100 to 200 V. 17. The method of claim 15 , wherein the vacuum chamber pressure is constant during deposition of the conformal conductive layer. 18. The method of claim 15 , wherein the power applied to the plasma is constant during deposition of the conformal conductive layer. 19. A method of forming a semiconductor structure comprising: forming a plurality of semiconductor fins on a substrate; forming a plurality of raised active regions on the semiconductor fins; depositing a first portion of a conductive layer over the raised active regions at a first ion energy; and depositing a second portion of the conductive layer over the first portion at a second ion energy, wherein the oxygen concentration within the deposited layer is less than 500 ppm.
Assignees
Inventors
Classifications
Physical vapour deposition [PVD] · CPC title
characterised by the source or drain electrodes · CPC title
- H10D30/024Primary
of fin field-effect transistors [FinFET] · CPC title
- H01L29/66795Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9859403B1 cover?
- During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/024. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).