Method for forming semiconductor structure with metallic layer over source/drain structure

Patent metadata

Field	Value
Publication number	US-9324820-B1
Application number	US-201514608805-A
Country	US
Kind code	B1
Filing date	Jan 29, 2015
Priority date	Oct 28, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes removing an unreacted portion of the metal layer on the metallic layer by an etching process. In addition, the etching process includes using an etchant including HF and propylene carbonate, and the volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:10 to about 1:10000.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming a source/drain structure over a substrate;
forming a metal layer on the source/drain structure;
reacting a portion of the metal layer with the source/drain structure to form a metallic layer on the source/drain structure; and
removing an unreacted portion of the metal layer on the metallic layer by an etching process;
wherein the etching process comprises using an etchant comprising HF and propylene carbonate, and a volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:10 to about 1:10000.

2. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the etching process is performed at a temperature in a range from about 20° C. to about 150° C.

3. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the metal layer is made of Ni, Co, Mo, Ti, Al, Sn, Pd, Pt, Au, Ag, or Cu.

4. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the source/drain structure is made of SiGe, Ge, GaAs, InAs, InGaAs, InAlAs, InP, InAlP, InN, GaN, InGaN, InGaP, GaSb, InSb, or InAsSbP.

5. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein an etching rate of the unreacted portion of the metal layer is greater than twenty times an etching rate of the metallic layer during the etching process.

6. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the portion of the metal layer reacts with the source/drain structure under a temperature no greater than 400° C.

7. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the source/drain structure is a raised source/drain structure formed in a fin structure over the substrate.

8. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the source/drain structure is a raised source/drain structure formed in a nanowire structure over the substrate.

9. A method for manufacturing a semiconductor structure, comprising:
forming a source/drain structure over a substrate;
forming a metal layer over the source/drain structure;
performing an annealing process so that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure;
removing an unreacted portion of the metal layer on the metallic layer by an etching process; and
forming a contact over the metallic layer,
wherein the etching process comprises using an etchant comprising HF and propylene carbonate, and a volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:50 to about 1:200.

10. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the annealing process is performed under a temperature no greater than 400° C.

11. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the etching process is performed at a temperature in a range from about 50° C. to about 100° C.

12. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the metal layer is made of Ni, Co, Mo, Ti, Al, Sn, Pd, Pt, Au, Ag, or Cu.

13. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein the source/drain structure is made of GaAs, InAs, InGaAs, InAlAs, InP, InAlP, InN, GaN, InGaN, InGaP, GaSb, InSb, or InAsSbP.

14. The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein an etching rate of the unreacted portion of the metal layer is greater than twenty times an etching rate of the metallic layer during the etching process.

15. A method for manufacturing a semiconductor structure, comprising:
forming a first source/drain structure over a substrate, wherein the first source/drain structure is made of group IIIA-VA alloy;
forming a second source/drain structure over the substrate, wherein the second source/drain structure is made of group IVA element or group IVA alloy;
forming a first metal layer over the first source/drain structure and a second metal layer over the second source/drain structure;
performing an annealing process so that a portion of the first metal layer reacts with the first source/drain structure to form a first metallic layer on the first source/drain structure and a portion of the second metal layer reacts with the second source/drain structure to form a second metallic layer on the second source/drain structure; and
performing an etching process to remove an unreacted portion of the first metal layer on the first metallic layer and an unreacted portion of the second metal layer on the second metallic layer;
wherein the etching process comprises using an etchant comprising HF and propylene carbonate, and a volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:50 to about 1:200.

16. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein the etching process is performed at a temperature in a range from about 50° C. to about 100° C.

17. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein the first metal layer and second metal layer are both made of Ni.

18. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein the first source/drain structure is made of GaAs, InAs, InGaAs, InAlAs, InP, InAlP, InN, GaN, InGaN, InGaP, GaSb, InSb, or InAsSbP.

19. The method for manufacturing a semiconductor structure as claimed in claim 18 , wherein the second source/drain structure is made of Ge or SiGe.

20. The method for manufacturing a semiconductor structure as claimed in claim 15 , wherein an etching rate of the unreacted portion of the metal layer is greater than twenty times an etching rate of the metallic layer during the etching process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kelly Andrew Joseph
• Oniki Yusuke

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0137

  the gate conductors being silicided · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title