Semiconductor device with a passivation layer

US9859395B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9859395-B2
Application numberUS-201414502882-A
CountryUS
Kind codeB2
Filing dateSep 30, 2014
Priority dateAug 29, 2012
Publication dateJan 2, 2018
Grant dateJan 2, 2018

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor device, the method comprising: providing a semiconductor body having a first surface; forming a first layer stack comprising an amorphous semi-insulating layer and a first nitride layer on the first surface, the first layer stack having an opening, wherein the amorphous semi-insulating layer comprises at least one of aSiC:H, aC:H, and aSi:H; forming a contact electrode in the opening; forming a second nitride layer on the first layer stack; and forming a first doped semiconductor region and a second doped semiconductor region, the first doped semiconductor region and the second doped semiconductor region forming a pn junction, wherein the contact electrode is connected to the second doped semiconductor region. 2. The method of claim 1 , wherein the amorphous semi-insulating layer comprises at least one of aSiC:H and aC:H. 3. The method of claim 1 , further comprising forming an intermediate layer on the first layer stack before forming the second nitride layer. 4. The method of claim 3 , wherein the intermediate layer has a hardness, the hardness of the intermediate layer being lower than a hardness of a material of the contact electrode and being higher than a hardness of one of the first and second nitride layers. 5. The method of claim 3 , wherein the intermediate layer comprises silicate glass. 6. The method of claim 3 , wherein the contact electrode comprises sidewalls and an upper surface, and wherein the intermediate layer and the second nitride layer are formed so as to cover the sidewalls and a section of the upper surface. 7. The method of claim 1 , wherein the contact electrode comprises at least one of aluminum, copper, an aluminum alloy, and a copper alloy. 8. The method of claim 1 , wherein the contact electrode is formed so as to overlap the first layer stack. 9. The method of claim 1 , wherein the contact electrode comprises sidewalls and an upper surface, and wherein the second nitride layer is formed so as to cover the sidewalls and a section of the upper surface. 10. A method of forming a semiconductor device, the method comprising: providing a semiconductor body having a first surface; forming a contact electrode arranged over the first surface; forming a passivation layer on the first surface adjacent the contact electrode, the passivation layer comprising a layer stack, wherein forming the layer stack comprises forming an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, an intermediate layer on the first nitride layer, and a second nitride layer on the intermediate layer, wherein the amorphous semi-insulating layer comprises at least one of aSiC:H, aC:H, and aSi:H; and forming a first doped semiconductor region and a second doped semiconductor region, the first doped semiconductor region and the second doped semiconductor region forming a pn junction, wherein the contact electrode is connected to the second doped semiconductor region. 11. The method of claim 10 , wherein the intermediate layer comprises one or more of the following: wherein the intermediate layer has a hardness that is lower than a hardness of a material of the contact electrode and is higher than a hardness of one of the first and second nitride layers, wherein the intermediate layer comprises silicate glass, and wherein the intermediate layer has a Young's modulus between 50 GPa and 70 GPa, and wherein a hardness of the intermediate layer is between 7 GPa and 10 GPa. 12. The method of claim 11 , wherein the intermediate layer has a hardness that is lower than a hardness of a material of the contact electrode and is higher than a hardness of one of the first and second nitride layers. 13. The method of claim 11 , wherein the intermediate layer comprises silicate glass. 14. The method of claim 11 , wherein the intermediate layer has a Young's modulus between 50 GPa and 70 GPa, and wherein a hardness of the intermediate layer is between 7 GPa and 10 GPa. 15. The method of claim 10 , wherein the amorphous semi-insulating layer comprises at least one of aSiC:H and aC:H. 16. The method of claim 10 , wherein the intermediate layer comprises at least one of USG, PSG, BSG, and BPSG. 17. The method of claim 10 , wherein the contact electrode has sidewalls and an upper surface, and wherein the intermediate layer and the second nitride layer cover the sidewalls and a section of the upper surface of the contact electrode. 18. The method of claim 10 , wherein the contact electrode has sidewalls and an upper surface, and wherein the second nitride layer covers the sidewalls and a section of the upper surface of the contact electrode. 19. The method of claim 10 , wherein the contact electrode comprises at least one of aluminum, copper, an aluminum alloy, and a copper alloy. 20. The method of claim 10 , wherein the contact electrode overlaps the amorphous semi-insulating layer and the first nitride layer. 21. The method of claim 10 , wherein the pn junction extends to the first surface, and wherein the passivation layer covers the pn junction on top of the first surface. 22. The method of claim 10 , wherein the contact electrode does not overlap the amorphous semi-insulating layer and the first nitride layer. 23. A method of forming a semiconductor device, the method comprising: providing a semiconductor body comprising a first surface; forming a contact electrode arranged on the first surface; forming a passivation layer on the first surface adjacent the contact electrode by forming a layer stack, wherein forming the layer stack comprises forming an amorphous semi-insulating layer on the first surface, wherein the amorphous semi-insulating layer comprises at least one of aSiC:H, aC:H, and aSi:H, forming a first nitride layer on the amorphous semi-insulating layer, and forming a second nitride layer on the first nitride layer; and forming a first doped semiconductor region and a second doped semiconductor region, the first doped semiconductor region and the second doped semiconductor region forming a pn junction, wherein the contact electrode is connected to the second doped semiconductor region. 24. The method of claim 23 , further comprising: forming a doped semiconductor region contacted by the contact electrode; and forming a Schottky junction between the contact electrode and the doped semiconductor region. 25. The method of claim 23 , further comprising forming an intermediate layer between the first nitride layer and the second nitride layer. 26. The method of claim 25 , wherein the intermediate layer comprises silicate glass. 27. The method of claim 25 , wherein the intermediate layer comprises USG, PSG, BSG, or BPSG. 28. The method of claim 25 , wherein the contact electrode has sidewalls and an upper surface, and wherein the intermediate layer and the second nitride layer cover the sidewalls and a section of the upper surface of the contact electrode. 29. The method of claim 23 , wherein the contact electrode comprises at least one of aluminum, copper, an aluminum alloy, and a copper alloy. 30. The method of claim 23 , wherein the contact electrode overlaps the amorphous semi-insulating layer and the first nitride layer. 31. The method of claim 23 , wherein th

Assignees

Inventors

Classifications

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

  • composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

  • Porous materials · CPC title

  • of conductive or resistive materials · CPC title

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What does patent US9859395B2 cover?
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride laye…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W74/137. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).