High reliability wafer level semiconductor packaging

US9859180B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9859180-B2
Application numberUS-201615174450-A
CountryUS
Kind codeB2
Filing dateJun 6, 2016
Priority dateFeb 17, 2016
Publication dateJan 2, 2018
Grant dateJan 2, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for making a semiconductor package, the method comprising: providing a semiconductor wafer and a glass wafer; forming a trench around a perimeter of one or more semiconductor die of the semiconductor wafer; forming a trench corresponding with the trench formed around the perimeter of the one or more semiconductor die in the glass wafer; applying adhesive into the trench of the semiconductor wafer and into the trench in the glass wafer; coupling the glass wafer to the semiconductor wafer by aligning the trench of the semiconductor wafer with the trench of the glass wafer and using the adhesive in the trenches to bond the semiconductor wafer to the glass wafer, the glass wafer forming one or more corresponding lids for the one or more semiconductor die; singulating the one or more semiconductor die and the corresponding one or more lids at the trench in the semiconductor wafer to form one or more semiconductor packages; coupling a redistribution layer to each of the one or more semiconductor packages; and coupling a plurality of ball mounts to each redistribution layer of the one or more semiconductor packages. 2. The method of claim 1 , wherein the trenches are formed through one of stencil printing, sawing, lasering, wet etching, dry etching and any combination thereof. 3. The method of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof. 4. The method of claim 1 , wherein the adhesive is applied by one of dispensing, spin coating, lithography, spray coating, stencil printing and any combination thereof. 5. The method of claim 1 , further comprising partially curing the adhesive before coupling the glass wafer to the semiconductor wafer. 6. The method of claim 1 , further comprising coupling the glass wafer and the semiconductor wafer using one of heat compression, ultraviolet light exposure, and any combination thereof. 7. A method for making a semiconductor package, the method comprising: providing a semiconductor wafer and a glass wafer; forming a trench around a perimeter of one or more semiconductor die of the semiconductor wafer; forming a trench corresponding with the trench formed around the perimeter of the one or more semiconductor die in the glass wafer; applying adhesive into the trench of the semiconductor wafer and into the trench in the glass wafer; coupling the glass wafer to the semiconductor wafer by aligning the trench of the semiconductor wafer with the trench of the glass wafer and using the adhesive in the trenches to bond the semiconductor wafer to the glass wafer, the glass wafer forming one or more corresponding lids for the one or more semiconductor die; and singulating the one or more semiconductor die and the corresponding one or more lids at the trench in the semiconductor wafer to form one or more semiconductor packages. 8. The method of claim 7 , wherein the trenches are formed through one of stencil printing, sawing, lasering, wet etching, dry etching and any combination thereof. 9. The method of claim 7 , wherein the adhesive is selected from the group consisting of thermal curable resin, epoxy, ultraviolet light curable resin and any combination thereof. 10. The method of claim 7 , wherein the adhesive is applied by one of dispensing, spin coating, lithography, spray coating, stencil printing and any combination thereof. 11. The method of claim 7 , further comprising partially curing the adhesive before coupling the glass wafer to the semiconductor wafer. 12. The method of claim 7 , further comprising coupling the glass wafer and the semiconductor wafer using one of heat compression, ultraviolet light exposure, and any combination thereof.

Assignees

Inventors

Classifications

  • characterised by their materials · CPC title

  • batch processes · CPC title

  • Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

  • Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

  • hardening the adhesive by curing, e.g. thermosetting · CPC title

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Frequently asked questions

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What does patent US9859180B2 cover?
Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be l…
Who is the assignee on this patent?
Semiconductor Components Ind Llc
What technology area does this patent fall under?
Primary CPC classification H10W76/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).