Incremental parasitic extraction for coupled timing and power optimization

Patent metadata

Field	Value
Publication number	US-9858383-B2
Application number	US-201514973893-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

First claim

What is claimed is:

1. A method of optimizing a semiconductor device, the method comprising:
performing, by a computer system, a first noise analysis on at least one first net included with the semiconductor device with respect to at least one aggressor net of the semiconductor device located adjacent to the at least one first net;
performing, by the computer system, a first optimization activity on the at least one first net based on results of the first noise analysis;
generating, by the computer system, a first invalidation list based on the first optimization activity;
generating, by the computer system, a second invalidation list based on a type of the first optimization action, wherein the type of the first optimization action includes re-routing of at least one of a promoted or demoted net to define a new route, and wherein the second invalidation list includes at least one new net coupled to the new route;
adding the second invalidation list to the first invalidation list; and
processing, by the computer system, the first and second invalidation lists and performing an extraction and noise analysis process on the first and second invalidation lists so as to determine capacitance information and resistance information that defines at least one new RC network of the semiconductor device and associated noise analysis results of the semiconductor device,
wherein the at least one new RC network is implemented in a semiconductor device design and the semiconductor device including the at least one new RC network is fabricated based on the semiconductor device design.

2. The method of claim 1 , wherein generating the first invalidation list includes identifying parasitic noise of the at least one aggressor net.

3. The method of claim 1 , wherein the first optimization activity includes at least one of layer promotion, layer demotion, buffer insertion, gate location change, gate type change, and logic equivalent port swap.

4. The method of claim 1 , further comprising optimizing the semiconductor device based on extracted information corresponding to the at least one new RC network and the associated noise analysis results.

5. The method of claim 4 , wherein the at least one new RC network includes the at least one first net and at least one new aggressor net excluded from the first optimization activity.

6. The method of claim 5 , wherein the extraction and noise analysis process includes computing parasitic coupling of the semiconductor device based on the second invalidation list.

7. The method of claim 6 , wherein the second optimization activity includes requesting timing optimization on the at least one first net.

8. An incremental parasitic extraction system, comprising:
a noise analysis module including an electronic hardware controller configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net located adjacent to the at least one first net;
an optimizer module including an electronic hardware controller configured to perform:
a first optimization activity on the at least one first net based on results of the first noise analysis,
to generate a first invalidation list based on the first optimization activity,
to generate a second invalidation list based on a type of the first optimization action, wherein the type of the first optimization action includes re-routing of at least one of a promoted or demoted net to define a new route, and wherein the second invalidation list includes at least one new net coupled to the new route, and
to add the second invalidation list to the first invalidation list; and
an extraction module including an electronic hardware controller configured to process the first and second invalidation lists and perform an extraction and noise analysis process on the first and second invalidation lists so as to determine capacitance information and resistance information that defines at least one new RC network and associated noise analysis results.

9. The system of claim 8 , wherein generating the first invalidation list includes identifying noise of the at least one aggressor net.

10. The system of claim 8 , wherein the first optimization activity includes at least one of layer promotion, layer demotion, buffer insertion, gate location change, gate type change, and logic equivalent port swap.

11. The system of claim 8 , further comprising optimizing the semiconductor device based on extracted information corresponding to the at least one new RC network and the associated noise analysis results.

12. The system of claim 11 , wherein the at least one new RC network includes the first net and at least one new aggressor net excluded from the first optimization activity.

13. The system of claim 12 , wherein the extraction and noise analysis process includes computing parasitic coupling based on the second invalidation list.

14. The system of claim 13 , wherein the second optimization activity includes requesting timing optimization on the at least one first net.

15. A computer program product to control an electronic device to optimize a semiconductor device, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic computer processor to control the electronic device to perform operations comprising:
performing, by the computer processor, a first noise analysis on at least one first net included with semiconductor device with respect to at least one aggressor net included with the semiconductor device located adjacent to the at least one first net;
performing, by the computer processor, a first optimization activity on the at least one first net based on results of the first noise analysis;
generating, by the computer processor, a first invalidation list based on the first optimization activity;
generating, by the computer processor, a second invalidation list based on a type of the first optimization action, wherein the type of the first optimization action includes re-routing of at least one of a promoted or demoted net to define a new route, and wherein the second invalidation list includes at least one new net coupled to the new route;
adding the second invalidation list to the first invalidation list; and
processing, by the computer processor, the first and second invalidation lists and performing an extraction and noise analysis process on the first and second invalidation lists so as to determine capacitance information and resistance information that defines at least one new RC network of the semiconductor device and associated noise analysis results corresponding to the semiconductor device,
wherein the at least one new RC network is implemented in a semiconductor device design and the semiconductor device including the at least one new RC network is fabricated based on the semiconductor device design.

16. The computer program product of claim 15 , wherein generating the first invalidation list includes identifying noise of the at least one aggressor net.

17. The computer program product of claim 15 , wherein the first optimization activity includes at least one of layer promotion, layer demotion, buffer insertion, gate location change, gate type change, and logic equivalent port swap.

18. The computer program product of claim 15 , further comprising optimizing the semiconductor device based on extracted information corresponding to the at least one new RC network and the associated noise analysis results.

19. The computer

Assignees

• IBM

Inventors

• Kalafala Kerim
• Ko Tsz-Mei
• Ledalla Ravichander
• Lee Alice H
• Matheny Adam P
• Neves Jose L
• Schaeffer Gregory M

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title