Incremental parasitic extraction for coupled timing and power optimization
US-10169526-B2 · Jan 1, 2019 · US
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Ledalla Ravichander patents
Ledalla Ravichander is listed as an inventor on 7 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ledalla Ravichander |
| Total patents | 7 |
| First publication | May 17, 2016 |
| Latest publication | Jan 1, 2019 |
Notable patents
Publications ranked by popularity score, then publication date.
Incremental parasitic extraction for coupled timing and power optimization
US-2018068052-A1 · Mar 8, 2018 · US
Incremental parasitic extraction for coupled timing and power optimization
US-9858383-B2 · Jan 2, 2018 · US
Incremental parasitic extraction for coupled timing and power optimization
US-2017177784-A1 · Jun 22, 2017 · US
Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints
US-9607124-B2 · Mar 28, 2017 · US
Method of Hierarchical Timing Closure Employing Dynamic Load-Sensitive Feedback Constraints
US-2016314236-A1 · Oct 27, 2016 · US
Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions
US-9342639-B1 · May 17, 2016 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 7 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2119/12 | 7 |
| G06F30/398 | 7 |
| G06F17/5081 | 7 |
| G06F30/367 | 6 |
| G06F2119/06 | 4 |