Constraint-driven pin optimization for hierarchical design convergence

Patent metadata

Field	Value
Publication number	US-9858377-B2
Application number	US-201514936920-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Nov 10, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

First claim

What is claimed is:

1. A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, the method comprising:
providing, using a processor implementing a unit level controller, an indication of candidate pins among a plurality of pins of a plurality of macros, the candidate pins being permitted to be moved and the plurality of macros being part of a unit that includes the unit level controller such that the unit is at a higher hierarchical level than the plurality of macros;
providing, using the processor implementing the unit level controller, constraints on a range of movement of one or more of the plurality of pins; and
performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints provided by the unit level controller to generate pin locations and timing results, wherein the chip design resulting from the physical synthesis is used to fabricate an integrated circuit or cause the integrated circuit to be fabricated.

2. The computer-implemented method according to claim 1 , further comprising providing, using the processor, physical and timing boundary conditions for the plurality of macros.

3. The computer-implemented method according to claim 1 , wherein the providing the constraints includes providing one or more types of constraints.

4. The computer-implemented method according to claim 3 , wherein the providing the constraints includes providing reach-based region constraints for at least one of the one or more of the plurality of pins, each reach-based region constraint limiting the movement of the respective at least one of the one or more of the plurality of pins to a two-dimensional range within the respective macro among the plurality of macros.

5. The computer-implemented method according to claim 3 , wherein the providing the constraints includes providing wire-based region constraints for at least one of the one or more of the plurality of pins, each wiring-based region constraint limiting the movement of the respective at least one of the one or more of the plurality of pins to a range in one dimension within the respective macro among the plurality of macros to ensure alignment with another pin among the plurality of pins.

6. The computer-implemented method according to claim 3 , wherein the providing the constraints includes providing unit timing, wiring, and buffering based constraints for at least one of the one or more of the plurality of pins, each unit timing, wiring, and buffering based constraint indicating relative freedom of the movement of the respective at least one of the one or more of the plurality of pins relative to others of the at least one of the one or more of the plurality of pins.

7. The computer-implemented method according to claim 6 , wherein the unit timing, wiring, and buffering based constraints indicate a greater relative freedom of the movement for one of the at least one of the one or more of the plurality of pins associated with a more timing critical path than for another of the at least one of the one or more of the plurality of pins associated with a less timing critical path.

8. A system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization, the system comprising:
a unit level controller of a unit configured to indicate candidate pins among a plurality of pins of a plurality of macros that may be moved and constraints on a range of movement of one or more of the plurality of pins, wherein the plurality of macros are part of the unit such that the unit is at a higher hierarchical level than the plurality of macros;
the plurality of macros configured to perform macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing; and
a component configured to fabricate an integrated circuit resulting from the physical synthesis or cause the integrated circuit to be fabricated.

9. The system according to claim 8 , wherein the unit level controller is further configured to provide physical and timing boundary conditions for the plurality of macros.

10. The system according to claim 8 , wherein the unit level controller provides one or more types of constraints.

11. The system according to claim 10 , wherein the unit level controller provides reach-based region constraints for at least one of the one or more of the plurality of pins, each reach-based region constraint limiting the movement of the respective at least one of the one or more of the plurality of pins to a two-dimensional range within the respective macro among the plurality of macros.

12. The system according to claim 10 , wherein the unit level controller provides wire-based region constraints for at least one of the one or more of the plurality of pins, each wiring-based region constraint limiting the movement of the respective at least one of the one or more of the plurality of pins to a range in one dimension within the respective macro among the plurality of macros to ensure alignment with another pin among the plurality of pins.

13. The system according to claim 10 , wherein the unit level controller provides unit timing, wiring, and buffering based constraints for at least one of the one or more of the plurality of pins, each unit timing, wiring, and buffering based constraint indicating relative freedom of the movement of the respective at least one of the one or more of the plurality of pins relative to others of the at least one of the one or more of the plurality of pins.

14. A computer program product for performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
providing, at a hierarchical level of a unit, an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, wherein the plurality of macros are part of the unit such that the plurality of macros is at a lower hierarchical level than the unit;
providing constraints on a range of movement of one or more of the plurality of pins; and
performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results, wherein the chip design resulting from the physical synthesis is used to fabricate an integrated circuit or cause the integrated circuit to be fabricated.

15. The computer program product according to claim 14 , further comprising providing, using the processor, physical and timing boundary conditions for the plurality of macros.

16. The computer program product according to claim 14 , wherein the providing the constraints includes providing one or more types of constraints.

17. The computer program product according to claim 16 , wherein the providing the constraints includes providing reach-based region constraints for at least one of the one or more of the plurality of pins, each reach-based region constraint limiting the movement of the respective at least one of the one or more of the plurality of pins to a two-dimensional range within the respective macro among the plurality of macros.

18. The computer program product according to claim 16 , wherein the providing the constraints includes providing wire-based region constraints for at least one of the

Assignees

• IBM

Inventors

• Berry Christopher J
• Darden Randall J
• Jatkowski Adam R
• Palumbo Joseph J
• Ramji Shyam
• Saha Sourav
• Schell Timothy A
• St Juste Eddy

Classifications

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title