Synthesis tuning system for VLSI design optimization

Patent metadata

Field	Value
Publication number	US-9529951-B2
Application number	US-201414290886-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	May 29, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

In one aspect, a method for tuning input parameters to a synthesis program is provided which includes the steps of: (a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function; (b) individually running synthesis jobs in parallel for each of the parameter settings in the subset; (c) analyzing results from a current iteration and prior iterations, if any, using the cost function; (d) using the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings; (e) running synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and (f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met.

First claim

What is claimed is:

1. A method for tuning input parameters to a synthesis program, the method comprising the steps of:
(a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function;
(b) individually running, using a processor device, synthesis jobs in parallel for each of the parameter settings in the subset;
(c) analyzing, using the processor device, results from a current iteration and prior iterations, if any, using the tuning optimization cost function;
(d) using the results from the current iteration and the prior iterations, if any, to create, using the processor device, combinations of the parameter settings;
(e) running, using the processor device, synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and
(f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met, wherein the synthesis program is a circuit synthesis program and the parameter settings are circuit synthesis parameter settings that are implemented in manufacturing integrated circuits, and wherein the exit criteria comprises one or more of: i) a predetermined number of iterations have been performed and ii) an iteration fails to improve results from one or more previous iterations.

2. The method of claim 1 , wherein the tuning optimization cost function represents multiple design metrics with a single cost number.

3. The method of claim 1 , wherein the tuning optimization cost function is expressed as a weighted sum of the design metrics.

4. The method of claim 1 , wherein the step (c) of analyzing the results is performed after either i) all of the synthesis jobs in the step (b) have completed, 2) a user-specified percentage of the synthesis jobs in the step (b) have completed, or 3) a predetermined time limit is reached.

5. The method of claim 1 , wherein the step (c) of analyzing the results comprises the step of:
ranking the results, based on the tuning optimization cost function, from a lowest cost, best result, to a highest cost, worst result.

6. The method of claim 1 , wherein one or more of the parameter settings yield results a top N cost ranked of which, based on the tuning optimization cost function, are placed in a survivor set, and wherein the combinations of the parameter settings are created by combining each of the parameter settings in the survivor set with exactly one other of the parameter settings in the survivor set.

7. The method of claim 6 , wherein user input influences which of the results are placed in the survivor set.

8. The method of claim 6 , wherein the combinations of the parameter settings are created using formula-based guesses by either i) combining all of the parameter settings in the survivor set, or ii) combining N lowest cost parameter settings, or iii) combining all parameter settings that lower cost below a certain predetermined amount.

9. The method of claim 1 , further comprising the step of:
(g) maintaining an archive of historical data in which the results are stored.

10. The method of claim 9 , further comprising the steps of:
using the results to search the historical data in the archive to create the combinations of the parameter settings.

11. The method of claim 10 , further comprising the steps of:
using the results as a clustering signature to cluster the historical data in the archive.

12. The method of claim 1 , further comprising the step of:
(h) using designer rules from one or more users to either 1) suggest new synthesis parameters or 2) directly change synthesis output.

13. The method of claim 1 , further comprising the step of:
(i) reusing portions of synthesis jobs from one or more prior iterations that are common to at least one of the additional iterations.

14. An apparatus for tuning input parameters to a synthesis program, the apparatus comprising:
a memory; and
at least one processor device, coupled to the memory, operative to:
(a) select a subset of parameter settings for the synthesis program based on a tuning optimization cost function;
(b) individually run synthesis jobs in parallel for each of the parameter settings in the subset;
(c) analyze results from a current iteration and prior iterations, if any, using the tuning optimization cost function;
(d) use the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings;
(e) run synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and
(f) repeat the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met, wherein the synthesis program is a circuit synthesis program and the parameter settings are circuit synthesis parameter settings that are implemented in manufacturing integrated circuits, and wherein the exit criteria comprises one or more of: i) a predetermined number of iterations have been performed and ii) an iteration fails to improve results from one or more previous iterations.

15. The apparatus of claim 14 , wherein the step of analyzing the results comprises the step of:
ranking the results, based on the tuning optimization cost function, from a lowest cost, best result, to a highest cost, worst result.

16. A computer program product for tuning input parameters to a synthesis program, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
(a) select a subset of parameter settings for the synthesis program based on a tuning optimization cost function;
(b) individually run synthesis jobs in parallel for each of the parameter settings in the subset;
(c) analyze results from a current iteration and prior iterations, if any, using the tuning optimization cost function;
(d) use the results from current iteration and the prior iterations, if any, to create combinations of the parameter settings;
(e) run synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and
(f) repeat the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met, wherein the synthesis program is a circuit synthesis program and the parameter settings are circuit synthesis parameter settings that are implemented in manufacturing integrated circuits, and wherein the exit criteria comprises one or more of: i) a predetermined number of iterations have been performed and ii) an iteration fails to improve results from one or more previous iterations.

Assignees

• IBM

Inventors

• Gristede George D
• Ziegler Matthew M

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F17/5022

  Physics · mapped topic