Method and program product for designing source and mask for lithography

Patent metadata

Field	Value
Publication number	US-9857676-B2
Application number	US-201414892987-A
Country	US
Kind code	B2
Filing date	May 9, 2014
Priority date	May 27, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A system and method for optimizing (designing) a mask pattern, in which SMO and OPC are collaboratively used to exert a sufficient collaborative effect or are appropriately used in different manners.
The method for designing a source and a mask for lithography includes a step (S 1 ) of selecting a set of patterns; a step of performing source mask optimization (SMO) using the set of patterns, under an optical proximity correction (OPC) restriction rule which is used for selectively restricting shifting of an edge position of a polygon when OPC is applied to the set of patterns; and a step (S 3 , S 4 ) of determining a layout of the mask for lithography, by applying OPC to all patterns constituting the mask for lithography using the source optimized through the SMO.

First claim

The invention claimed is:

1. A method for designing a source and generating a mask for lithography, said method comprising:
selecting, using a hardware processor, a set of patterns corresponding to a mask used in a lithographic production of a circuit structure in a semiconductor wafer;
using said hardware processor to perform a source mask optimization (SMO) process using the set of patterns, under an optical proximity correction (OPC) restriction rule, said hardware processor applying said OPC restriction rule to selectively restrict a shifting of an edge position of a polygon of a mask pattern when applying an OPC to the set of patterns;
determining, using said hardware processor, a layout of the mask for lithography, by applying OPC to all patterns constituting the mask for lithography using the source optimized through the SMO process; and
generating a lithographic mask structure on a semiconductor wafer according to said determined mask layout.

2. The method according to claim 1 , further comprising:
performing said SMO process without applying the OPC restriction rule, on at least one pattern selected from the set of patterns, and
performing, using said hardware processor, under the OPC restriction rule, said SMO on the rest of the set of patterns.

3. The method according to claim 2 , wherein the performing said SMO process without applying the OPC restriction rule further comprises: using said hardware processor to perform said SMO process for a pattern for which an SMO computation result is not obtained within a pre-determined period.

4. The method according to claim 2 , wherein the performing said SMO process without applying the OPC restriction rule further comprises: using the hardware process to perform said SMO process using a frequency-domain mask shape obtained by performing Fourier transform on a spatial-domain mask shape for which the edge position of the polygon serves as a variable.

5. The method according to claim 2 , wherein the at least one pattern includes a pattern corresponding to a hotspot.

6. The method according to claim 1 , wherein the OPC restriction rule includes fixing at least one edge selected from among edges of a polygon for the set of patterns and fixing an edge of a sub-resolution assist feature (SRAF).

7. The method according to claim 6 , wherein the at least one edge includes an edge that is defined during OPC to be performed after the SMO is performed.

8. The method according to claim 6 , wherein the at least one edge includes an edge shorter than a pre-determined length.

9. The method according to claim 1 , further comprising:
applying, using a photolithographic exposure apparatus, an illumination condition optimized according to said SMO process, to the generated lithographic mask to form the circuit structure in said semiconductor wafer.

10. The method according to claim 9 , wherein the illumination condition, optimized according to said SMO process, includes a shape of a pixelated illumination source.

11. A computer program product for generating a mask structure used in photolithographic process, said computer program product comprising:
a non-transitory computer readable medium storing instructions that, when executed by at least one hardware processor, configure the at least one hardware processor to perform a method of:
selecting a set of patterns corresponding to a mask used in a lithographic production of a circuit structure in a semiconductor wafer;
performing a source mask optimization (SMO) process using the set of patterns, under an optical proximity correction (OPC) restriction rule, and applying said OPC restriction rule to selectively restrict a shifting of an edge position of a polygon of a mask pattern when applying an OPC to the set of patterns;
determining a layout of the mask for lithography, by applying OPC to all patterns constituting the mask for lithography using the source optimized through the SMO process; and
generating a lithographic mask structure on a semiconductor wafer according to said determined mask layout.

12. The computer program product according to claim 11 , wherein said method further comprises:
performing said SMO without applying the OPC restriction rule, on at least one pattern selected from the set of patterns, and
performing, under the OPC restriction rule, said SMO on the rest of the set of patterns.

13. The computer program product according to claim 12 , wherein the performing said SMO process without applying the OPC restriction rule is performed for a pattern for which an SMO computation result is not obtained within a pre-determined period.

14. The computer program product according to claim 12 , wherein the performing said SMO process without applying the OPC restriction rule is performed using a frequency-domain mask shape obtained by performing Fourier transform on a spatial-domain mask shape for which the edge position of the polygon serves as a variable.

15. The computer program product according to claim 12 , wherein the at least one pattern includes a pattern corresponding to a hotspot.

16. The computer program product according to claim 11 , wherein the OPC restriction rule includes fixing at least one edge selected from among edges of a polygon for the set of patterns and fixing an edge of a sub-resolution assist feature (SRAF).

17. The computer program product according to claim 16 , wherein the at least one edge includes an edge that is defined during OPC to be performed after the SMO is performed.

18. The computer program product according to claim 16 , wherein the at least one edge includes an edge shorter than a pre-determined length.

19. The computer program product according to claim 11 , wherein the method further comprises:
applying, using a photolithographic exposure apparatus, an illumination condition optimized according to said SMO process, to the generated lithographic mask to form the circuit structure in said semiconductor wafer.

20. The computer program product according to claim 19 , wherein the illumination condition, optimized according to said SMO process, includes a shape of a pixelated illumination source.

Assignees

• IBM

Inventors

• Inoue Tadanobu
• Melville David O
• Rosenbluth Alan E
• Sakamoto Masaharu
• Tian Kehan

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G03F7/70433

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title