Semiconductor device and structure

Patent metadata

Field	Value
Publication number	US-9853089-B2
Application number	US-201615224929-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Oct 12, 2009
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first memory cell comprising a first transistor;
a second memory cell comprising a second transistor,
wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor; and

a plurality of junctionless transistors,
wherein at least one of said junctionless transistors controls access to at least one of said memory cells.

2. A semiconductor according to claim 1 ,
wherein said junctionless transistors each comprise a single crystal channel.

3. A semiconductor according to claim 1 ,
wherein said first transistor comprises silicon and germanium atoms.

4. A semiconductor according to claim 1 , further comprising:
an electrically controlled resistive structure connected to a source or a drain of said first transistor.

5. A semiconductor according to claim 1 ,
wherein said first transistor comprises a silicided source and drain.

6. A semiconductor according to claim 1 , further comprising:
a third memory cell, and
an electronic circuit adapted to remap said third memory cell.

7. A semiconductor according to claim 1 , further comprising:
a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

8. A semiconductor device, comprising:
an electrically controlled resistive structure;
a first memory cell comprising a first transistor; and
a second memory cell comprising a second transistor,
wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and
wherein said electrically controlled resistive structure could be set to conduct a signal to said first transistor.

9. A semiconductor according to claim 8 ,
wherein said first transistor comprises a single crystal channel.

10. A semiconductor according to claim 8 ,
wherein said first transistor comprises a silicon and germanium atoms.

11. A semiconductor according to claim 8 ,
wherein said first transistor comprises a silicided source and drain.

12. A semiconductor according to claim 8 ,
wherein access to said first memory cell is controlled by at least one junctionless transistor.

13. A semiconductor according to claim 8 , further comprising:
a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

14. A semiconductor according to claim 8 , further comprising:
a memory control line,
wherein said memory control line has a direct contact with said first transistor.

15. A semiconductor device, comprising:
a first memory cell comprising a first transistor; and
a second memory cell comprising a second transistor,
wherein said second transistor overlays said first transistor and said second transistor is self-aligned to said first transistor, and
wherein said first transistor comprises a silicided source and drain.

16. A semiconductor according to claim 15 ,
wherein said first transistor comprises a single crystal channel.

17. A semiconductor according to claim 15 ,
wherein said first transistor comprises silicon and germanium atoms.

18. A semiconductor according to claim 15 , further comprising:
a memory peripherals circuits overlaying said second transistor or underneath said first transistor.

19. A semiconductor according to claim 15 ,
wherein access to said first memory cell is controlled by at least one junctionless transistor.

20. A semiconductor according to claim 15 , further comprising:
a memory control line,
wherein said memory control line has direct contact with said first transistor.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Sekar Deepak C
• Cronquist Brian
• Beinglass Israel
• Wurman Zeev

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title