Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9852986-B1
Application number	US-201615362035-A
Country	US
Kind code	B1
Filing date	Nov 28, 2016
Priority date	Nov 28, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is patterned into the mandrel layer. Mandrel spacers are formed self-aligned on sidewalls of the mandrels. A gapfill layer is disposed and planarized over the semiconductor structure. Non-mandrel pillars are formed over the planarized gapfill layer. Exposed portions of the gapfill layer are etched to form non-mandrel plugs preserved by the pillars. The pillars are removed to form a pattern, the pattern including the non-mandrel plugs. The pattern is utilized to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack. The array includes non-mandrel dielectric structures formed from the non-mandrel plugs.

First claim

What is claimed is:

1. A method comprising:
providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon;
patterning an array of mandrels into the mandrel layer such that the array of mandrels includes:
a plurality of minimum width mandrels having a minimum width and a minimum mandrel pitch, and
a wide mandrel section having a width and a length that are at least equal to two minimum mandrel pitches;
patterning a plurality of mandrel openings into the array of mandrels, the mandrel openings having at least a minimum opening width and having a minimum opening length required to provide a minimum mandrel continuity cut through a mandrel metal line having a minimum metal line width;
patterning a transition region opening into the array of mandrels, the transition region opening having a width and a length that are at least equal to two minimum mandrel pitches, the transition region opening being disposed between, and adjacent to, the wide mandrel section and at least two minimum width mandrels;
forming mandrel spacers self-aligned on sidewalls of the mandrels;
disposing and planarizing a gapfill layer over the semiconductor structure;
forming non-mandrel pillars over the planarized gapfill layer;
etching exposed portions of the gapfill layer to form non-mandrel plugs preserved by the pillars;
removing the pillars to form a pattern, the pattern including the non-mandrel plugs; and
utilizing the pattern to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack, the array including non-mandrel dielectric structures formed from the non-mandrel plugs.

2. The method of claim 1 comprising:
the pattern including a non-mandrel line plug preserved by a pillar; and
forming a non-mandrel dielectric line region from the non-mandrel line plug, the non-mandrel dielectric line region being disposed between, and self-aligned with, two adjacent mandrel metal lines of the pattern.

3. The method of claim 1 comprising:
the pattern including a non-mandrel ANA region plug;
forming a non-mandrel dielectric ANA region from the non-mandrel ANA region plug.

4. The method of claim 1 comprising:
the pattern including a non-mandrel cut plug;
forming a non-mandrel dielectric continuity cut from the non-mandrel cut plug, the non-mandrel dielectric continuity cut being disposed within a non-mandrel metal line of the pattern.

5. The method of claim 1 comprising:
the pattern including a non-mandrel transition region plug;
forming a non-mandrel dielectric transition region from the non-mandrel transition region plug, the non-mandrel dielectric transition region being disposed between tip ends of a plurality of mandrel and non-mandrel metal lines having a minimum width and a wide mandrel metal line having a width that is larger than the minimum width.

6. The method of claim 1 wherein the array of mandrel and non-mandrel metal lines have a minimum pitch that is equal to or less than one of 80 nm and 40 nm.

7. The method of claim 1 wherein the dielectric stack includes an ultra-low k (ULK) layer, and the array of metal interconnection lines is disposed in the ULK layer.

8. The method of claim 1 comprising disposing a spacer layer over the array of mandrels, the spacer layer having a predetermined spacer layer thickness that is greater than or equal to half the minimum opening length of a mandrel opening, wherein the spacer layer fills the plurality of mandrel openings to form a plurality of mandrel cut plugs and does not fill the transition region opening.

9. The method of claim 8 comprising etching the spacer layer to form the mandrel spacers.

10. The method of claim 9 comprising:
filling the transition region opening with the gapfill layer;
forming a non-mandrel pillar over the filled transition region opening;
etching exposed portions of the gapfill layer to form a non-mandrel transition region plug preserved by the non-mandrel pillar over the filled transition region opening;
forming a non-mandrel dielectric transition region within the array of metal interconnections lines from the non-mandrel transition region plug; and
forming mandrel continuity cuts within the mandrel metal lines of the array of metal interconnection lines from the mandrel cut plugs.

Assignees

• Globalfoundries Inc

Inventors

• Stephens Jason Eugene
• Bouche Guillaume

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L21/3081

  Electricity · mapped topic