Cell layout for SRAM FinFET transistors

Patent metadata

Field	Value
Publication number	US-9012287-B2
Application number	US-201313788954-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	Nov 14, 2012
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The at least one active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

First claim

What is claimed is:

1. A method of forming a semiconductor device having a static random-access memory (SRAM) cell array, wherein each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs, the method comprising:
patterning a plurality of fins including active fins and dummy fins, wherein each PG FinFET shares at least one active fin with a PD FinFET, wherein no dummy fin is disposed between PU FinFETs in a memory cell, a dummy fin is disposed be…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liaw Jhon Jhy

Classifications

• H10D84/0158

  Electricity · mapped topic

• H10D89/10

  Electricity · mapped topic

• H10D86/215

  Electricity · mapped topic

• H10D86/011

  Electricity · mapped topic

• H10D84/853

  Electricity · mapped topic