Method for forming fine pattern of semiconductor device using double spacer patterning technology

Patent metadata

Field	Value
Publication number	US-8999848-B2
Application number	US-201213679518-A
Country	US
Kind code	B2
Filing date	Nov 16, 2012
Priority date	Jul 12, 2012
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.

First claim

What is claimed is:

1. A method of forming a fine pattern of a semiconductor device, the method comprising:
forming a second layer over a first layer;
forming a partition pattern over the second layer;
forming first spacers over sidewalls of the partition pattern;
forming a first gap-fill layer filling between the first spacers;
removing the first spacers;
etching the second layer using the partition pattern and the first gap-fill layer as an etch mask to form a first pa…

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Lyoung
• Bok Cheol Kyu
• Kim Won Kyu

Classifications

• H10P50/695

  Electricity · mapped topic

• H10D64/01328 Primary

  Electricity · mapped topic

• H10W70/05 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L27/11531

  Electricity · mapped topic