Semiconductor devices with through electrodes and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9852965-B2
Application number	US-201615204632-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Aug 13, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having electrically active and electrically inactive surfaces facing each other:
a through electrode passing through the substrate and extending from the electrically active surface to the electrically inactive surface;
an interconnection line provided on the electrically active surface of the substrate; and
a first via provided between the through electrode, and the interconnection line that electrically connects the through electrode to the interconnection line,
wherein the first via is a ring-shaped structure and at least a portion of the first via extends at a circumference of the through electrode.

2. The semiconductor device of claim 1 , wherein the through electrode fills at least a portion of a via hole in the substrate,
wherein the via hole has an inner surface defining an interface between the substrate and the through electrode,
the first via has a top surface adjacent to the interconnection line and a bottom, surface adjacent to the through electrode, and
the bottom surface of the first via overlaps the inner surface of the via hole.

3. The semiconductor device of claim 2 , wherein the through electrode extends beyond the electrically active surface of the substrate to fill an internal space at least partially defined by the first via.

4. The semiconductor device of claim 1 , further comprising a second via provided inside an area defined by the first via, wherein the second via electrically connects the through electrode to the interconnection line.

5. The semiconductor device of claim 4 , wherein the second via is a pillar-shaped structure that extends between the interconnection line and the through electrode.

6. The semiconductor device of claim 4 , wherein the second via is a ring-shaped structure that extends between the interconnection line and the through electrode, and at least a portion of the second via extends at a circumference of the through electrode.

7. The semiconductor device of claim 4 , wherein the through electrode has a top surface facing the interconnection line, and
the top surface of the through electrode has an uneven shape.

8. The semiconductor device of claim 4 , wherein the through electrode extends beyond the electrically active surface of the substrate to fill a space between the first via and the second via.

9. The semiconductor device of claim 1 , further comprising a third via that is provided outside the first via and is electrically connected to the interconnection line.

10. The semiconductor device of claim 9 , wherein the third via is a ring-shaped structure that is between the substrate and the interconnection line and encloses the first via.

11. The semiconductor device of claim 9 , wherein the third via is a circular-pillar-shaped structure that is between the substrate and the interconnection line.

12. A semiconductor device, comprising;
a semiconductor substrate having electrically active and electrically inactive surfaces facing each other;
an interlayered insulating layer provided on the electrically active surface of the semiconductor substrate,
a metal line provided in the interlayered insulating layer;
a via hole vertically penetrating the semiconductor substrate from the electrically active surface to the electrically inactive surface;
a through electrode filling the via hole and vertically extending from the electrically active surface to the electrically inactive surface; and
a main via provided in the interlayered insulating layer that electrically connects the through electrode to the metal line,
wherein the main via has a hollow ring-shaped cylindrical structure that vertically extends from the metal line to the through electrode and at least a portion of the main via is along a circumference of the via hole and overlaps at least a portion of the via hole, when viewed in a plan view.

13. The semiconductor device of claim 12 , further comprising an auxiliary via that is provided in an empty space of the main via or outside the main via and is electrically connected to the metal line.

14. The semiconductor device of claim 13 , wherein the through electrode extends into a region between the auxiliary via and the main via and extends beyond the electrically active surface of the semiconductor substrate.

15. The semiconductor device of claim 12 , wherein the through electrode extends into the main via beyond the electrically active surface of the semiconductor substrate.

16. A semiconductor device comprising:
a substrate having electrically active and electrically inactive surfaces that face each other;
a through electrode that vertically extends through the substrate from the electrically active surface to the electrically inactive surface and, in a horizontal plane, the through electrode has a first perimeter; and
a first via on the electrically active surface of the substrate, the first via having an inner perimeter and an outer perimeter in the horizontal plane,
wherein the outer perimeter of the first via is greater than and surrounds the first perimeter of the through electrode.

17. The semiconductor device of claim 16 , wherein the inner perimeter of the first via is greater than or equal to the first perimeter of the through electrode and optionally the inner perimeter of the first via surrounds the first perimeter of the through electrode.

18. The semiconductor device of claim 16 , wherein the substrate includes an inner surface that vertically extends through the substrate from the electrically active surface to the electrically inactive surface, and the inner surface, in the horizontal plane, has a second perimeter, and
wherein the outer perimeter of the first via is greater than and surrounds the second perimeter, the inner perimeter of the first via is less than the second perimeter, and the second perimeter surrounds the inner perimeter.

19. The semiconductor device of claim 16 , wherein the first via has a hollow cylindrical shape.

20. The semiconductor device of claim 16 , further comprising a second via on the electrically active surface of the substrate and in an area surrounded by the outer and inner perimeters of the first via.

Assignees

• Lee Ho-Jin
• Park Byung Lyul
• Moon Kwangjin
• Park Jisoon
• An Jin Ho
• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jin
• Park Byung Lyul
• Moon Kwangjin
• Park Jisoon
• An Jin Ho

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/722

  between stacked chips · CPC title