Method of manufacturing semiconductor device for reducing grain size of polysilicon

Patent metadata

Field	Value
Publication number	US-9852912-B1
Application number	US-201615270638-A
Country	US
Kind code	B1
Filing date	Sep 20, 2016
Priority date	Sep 20, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate;
defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions;
treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and
depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate in the presence of the dielectric layer as the outermost layer exposed at the backside of the silicon substrate.

2. The method according to claim 1 , wherein the dielectric layer comprises oxides, nitrides or a combination thereof.

3. The method according to claim 1 , wherein the dielectric layer is a silicon oxide (SiO 2 ) layer, a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer.

4. The method according to claim 1 , wherein the isolation regions comprises isolation portions, and the active regions comprises polysilicon portions.

5. The method according to claim 4 , wherein before forming the polysilicon layer, the polysilicon portions and the dielectric layer are exposed at the front side and the backside of the silicon substrate, respectively.

6. The method according to claim 4 , wherein the polysilicon layer directly contacts the polysilicon portions at the front side after forming the polysilicon layer.

7. The method according to claim 1 , wherein the polysilicon layer is deposited in a furnace with a silane or disilane ambient.

8. The method according to claim 7 , further comprising:
providing a plurality of the silicon substrates in the furnace, wherein the active regions and the dielectric layer of each of the plurality of the silicon substrates are respectively exposed at the front side and the backside of the silicon substrate;
arranging the plurality of the silicon substrates by facing the dielectric layer to the active regions of adjacent silicon substrates; and
depositing the polysilicon layer on the isolation regions and the active regions at the front side of each of the plurality of the silicon substrates.

9. The method according to claim 1 , wherein the multiple layers comprises:
a first pad oxide layer and a first pad nitride layer formed on the front side of the silicon substrate, wherein the first pad nitride layer is formed on the first pad oxide layer; and
a second pad oxide layer and a second pad nitride layer formed on the backside of the silicon substrate, wherein the second pad nitride layer is formed on the second pad oxide layer.

10. The method according to claim 9 , wherein steps of defining the isolation regions and the active regions comprises:
patterning the first pad nitride layer, the first pad oxide layer, a gate oxide layer and the silicon substrate to form trenches and patterned stacks; and
forming an insulation layer on the trenches and the patterned stacks, followed by planarization.

11. The method according to claim 10 , wherein steps of treating the multiple layers comprise:
removing the first pad nitride layer and the second pad nitride layer; and
removing the first pad oxide layer (by single wafer clean), and remaining the dielectric layer as the outermost layer exposed at the backside of the silicon substrate.

12. A method for manufacturing a semiconductor device, comprising:
providing a silicon substrate having a front side and a backside, and isolation portions and polysilicon portions being formed and exposed at the front side of the silicon substrate, and at least a dielectric layer remained as an outermost layer exposed at the backside of the silicon substrate, wherein the polysilicon portions are separated by the isolation portions; and
depositing a polysilicon layer on the isolation portions and the polysilicon portions at the front side of the silicon substrate when the dielectric layer is exposed at the backside of the silicon substrate.

13. The method according to claim 12 , wherein the dielectric layer comprises oxides, nitrides or a combination thereof, and the polysilicon layer is deposited in a furnace.

14. The method according to claim 12 , wherein the dielectric layer comprises oxides, nitrides or a combination thereof.

15. The method according to claim 12 , wherein the isolation portions comprises oxides.

16. The method according to claim 12 , wherein the polysilicon layer directly contacts the polysilicon portions after forming the conductive layer.

17. The method according to claim 12 , further comprising:
providing a plurality of the silicon substrates in the furnace, wherein the polysilicon portions and the dielectric layer of each of the plurality of the silicon substrates are respectively exposed at the front side and the backside of the silicon substrate;
arranging the plurality of the silicon substrates by facing the dielectric layer to the polysilicon portions of adjacent silicon substrates; and
depositing the polysilicon layer on the isolation regions and the polysilicon portions at the front side of each of the plurality of the silicon substrates.

Assignees

• United Microelectronics Corp

Inventors

• Zhang Sheng
• Yi Liang
• Ding Wen-Bo
• Pang Chien-Kee
• Chen Yu-Yang

Classifications

• H01L21/28273 Primary

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title