Analog dithering to reduce vertical fixed pattern noise in image sensors

Patent metadata

Field	Value
Publication number	US-9848152-B1
Application number	US-201615277859-A
Country	US
Kind code	B1
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation;
a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

2. The apparatus of claim 1 , wherein the offset voltage is temporally randomly added to the first reference voltage.

3. The apparatus of claim 1 , wherein the analog dithering circuit randomly capacitively couples one of a third or fourth reference voltage to an input of the ramp generator circuit, the input of the ramp generator circuit additionally coupled to receive the first reference voltage, and wherein the offset voltage changes based on the one of the third or fourth reference voltages randomly coupled to the input of the ramp generator circuit.

4. The apparatus of claim 3 , wherein the analog dithering circuit comprises:
a first switch coupled between the third reference voltage and a first node, wherein the first switch is selectively controlled by a second control signal;
a second switch coupled between the fourth reference voltage and the first node, wherein the second switch is selectively controlled by an inverse of the second control signal;
a first capacitor coupled between the input of the ramp generator circuit and ground, the second capacitor coupled to store the first reference voltage; and
a second capacitor coupled between the input of the ramp generator circuit and the first node,
wherein the second control signal randomly changes in response to a random binary signal during the analog to digital conversion, and wherein the random changes randomly coupled the third or fourth reference voltage to the first node.

5. The apparatus of claim 4 , wherein the analog dithering circuit further comprises:
a logic gate coupled to receive a random binary signal and an inverse of a first control signal, an output of the logic gate changing in response to the random binary signal and the inverse of the first control signal, wherein the output of the logic gate is the second control signal; and
a random binary signal generator coupled to provide the random binary signal.

6. The apparatus of claim 5 , wherein the logic gate is an AND gate.

7. The apparatus of claim 5 , wherein the random binary signal generator circuit is a linear feedback shift register including a plurality of flip flops coupled in series and coupled to receive a plurality of intermediate outputs as an input via an exclusive NOR gate, and wherein an output of the linear feedback shift register is the random binary signal.

8. The apparatus of claim 5 , wherein the offset voltage is based at least in part on the first and second capacitors.

9. An imaging system, comprising:
an array of pixels, wherein a pixel in the array of pixels is to receive image light and provide image charge in response;
column readout circuitry coupled to receive the image charge and provide a digital representation of the image charge in response to a digital to analog conversion operation, the column readout circuitry including:
a comparator coupled to receive the image data and a ramp voltage, and provide the digital representation of the image charge in response;
a ramp generator coupled to receive a first reference voltage and provide the ramp voltage in response; and
an analog dithering circuit coupled to randomly add an offset voltage to the first reference voltage during the analog to digital conversion operation.

10. The imaging system of claim 9 , wherein the randomly added offset voltage appears as noise on the ramp voltage.

11. The imaging system of claim 9 , wherein the offset voltage is either zero, or a voltage level that is less than a voltage level of vertical fixed pattern noise.

12. The imaging system of claim 9 , wherein the analog dithering circuit includes:
a first switch coupled between the third reference voltage and a first node, wherein the first switch is selectively controlled by a second control signal;
a second switch coupled between the fourth reference voltage and the first node, wherein the second switch is selectively controlled by an inverse of the second control signal;
a first capacitor coupled between the input of the ramp generator circuit and ground, the second capacitor coupled to store the first reference voltage; and
a second capacitor coupled between the input of the ramp generator circuit and the first node,
wherein the second control signal randomly changes in response to a random binary signal during the analog to digital conversion, and wherein the random changes randomly coupled the third or fourth reference voltage to the first node, and
wherein the offset voltage is based at least in part on the first and second capacitors.

13. The imaging system of claim 12 , wherein the analog dithering circuit further comprises:
an AND gate coupled to receive a random binary signal and an inverse of a first control signal, an output of the AND gate changing in response to the random binary signal and the inverse of the first control signal, wherein the output of the AND gate is the second control signal; and
a random binary signal generator coupled to provide the random binary signal.

14. The imaging system of claim 13 , wherein the random binary signal generator is a linear feedback shift register including 32 D flip flops, wherein an input to the linear feedback shift register is an output of an exclusive NOR gate coupled to receive outputs from four of the 32 D flip flops, and wherein an output of the linear feedback shift register is the random binary signal.

15. The imaging system of claim 12 , wherein the random binary signal is pseudo random.

16. A method to add random noise to a ramp voltage, comprising:
receiving a first reference voltage at an input of a ramp generator;
randomly adding an offset voltage to the first reference voltage during an analog to digital conversion operation;
receiving a second reference voltage at a first input of a comparator, wherein the second reference voltage is provided by the ramp generator and includes the randomly added offset voltage;
receiving an image data at a second input of the comparator; and
comparing the image data to the second reference voltage to provide a digital representation of the image data during the analog to digital conversion operation.

17. The method of claim 16 , wherein randomly adding an offset voltage to the first reference voltage during an analog to digital conversion operation comprises:
randomly capacitively coupling one of a third reference voltage or a fourth reference voltage to the input of the ramp generator.

18. The method of claim 17 , wherein randomly capacitively coupling one of a third reference voltage or a second reference voltage to the input of the ramp generator comprises:
randomly coupling a first side of a first capacitance to either the third reference voltage or the fourth reference voltage in response to a random binary signal, wherein a second side of the first capacitance is coupled to the input of the ramp generator.

19. The method of claim 18 , wherein the offset voltage is based at least in part on the first capacitance and a second capacitance, the second capacitance coupled between to the input of the ramp generator and ground, and wherein the seco

Assignees

• Omnivision Tech Inc

Inventors

• Lin Yingkan
• Yang Yu-Shen
• Deng Liping

Classifications

• H03M1/0639 Primary

  using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201) · CPC title

• H04N25/00 Primary

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03K4/502

  the capacitor being charged from a constant-current source · CPC title

• H04N5/378 Primary

  Electricity · mapped topic