Monitoring and control of reference clocks to reduce bit error ratio

Patent metadata

Field	Value
Publication number	US-9520965-B2
Application number	US-201414587477-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A method for reducing a frequency error, including: applying a plurality of dither values to a local reference clock over a first time interval; sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, where the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; tracking a plurality of errors from sampling the first plurality of data values; and adjusting, based on the plurality of errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

First claim

What is claimed is:

1. A method for reducing a frequency error, comprising:
applying a plurality of dither values to a local reference clock over a first time interval by:
applying, by modifying a divider, a first set of positive dither values during a first half of the first time interval, and
applying, by modifying the divider, a second set of negative dither values during a second half of the first time interval;
sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, wherein the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock;
tracking a plurality of bit errors from the sampling of the first plurality of data values; and
adjusting, based on the plurality of bit errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

2. The method of claim 1 , wherein the first set of positive dither values has a maximum dither value of 1.0 parts per million (PPM), wherein two consecutive positive dither values have a step size of 100 parts per billion (PPB), and wherein the plurality of dither values form a triangular wave.

3. The method of claim 1 , wherein applying the first set of positive dither values comprises:
modifying a numerator of the divider in a clock synthesizer integrated circuit of the local reference clock.

4. The method of claim 1 , wherein tracking the plurality of bit errors comprises:
counting a first number of bit errors during the first half of the first time interval;
counting a second number of bit errors during the second half of the first time interval; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the adjusting of the frequency of the local reference clock is based on the comparison.

5. The method of claim 1 , further comprising:
applying, after adjusting the frequency of the local reference clock, the first set of positive dither values to the local reference clock during a first half of a second time interval;
applying, after adjusting the frequency of the local reference clock, the second set of negative dither values to the local reference clock during a second half of the second time interval;
sampling, during the second time interval and using the local reference clock, a second plurality of data values received over the asynchronous link, wherein the second plurality of data values are transmitted over the asynchronous link based on the remote reference clock;
counting a first number of bit errors from the sampling of the second plurality of data values during the first half of the second time interval;
counting a second number of bit errors from the sampling of the second plurality of data values during the second half; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the comparison indicates that the first number of bit errors and the second number of bit errors are balanced.

6. The method of claim 1 , further comprising:
issuing, by a first line module comprising the local reference clock, an alert based on repeated adjustments to the local reference clock, wherein the remote reference clock is located in a switch module connected to the first line module and a second line module, and
wherein failure of a crystal in the local reference clock is detected based on the alert from the first line module and no alert from the second line module.

7. The method of claim 1 , further comprising:
issuing, by a first line module comprising the local reference clock, a first alert based on repeated adjustments to the local reference clock, wherein the remote reference clock is located in a switch module connected to the first line module and a second line module, wherein the second line module issues a second alert, and
wherein failure of a crystal in the remote reference clock is detected based on the first alert and the second alert.

8. A non-transitory computer readable medium (CRM) comprising instructions stored thereon for reducing a frequency error, the instructions when executed by a processor causes the processor to:
apply a plurality of dither values to a local reference clock over a first time interval by:
applying, by modifying a divider, a first set of positive dither values during a first half of the first time interval, and
applying, by modifying the divider, a second set of negative dither values during a second half of the first time interval;

track a plurality of bit errors from sampling a first plurality of data values received over an asynchronous link,
wherein the first plurality of data values are sampled during the first time interval using the local clock reference, and
wherein the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; and
adjust, based on the plurality of bit errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

9. The non-transitory CRM of claim 8 , wherein the first set of positive dither values has a maximum dither value of 1.0 parts per million (PPM), and wherein two consecutive positive dither values have a step size of 100 parts per billion (PPB).

10. The non-transitory CRM of claim 8 , wherein the application of the first set of positive dither values comprises:
modifying a numerator in the divider in a clock synthesizer integrated circuit of the local reference clock.

11. The non-transitory CRM of claim 8 , wherein the tracking of the plurality of bit errors comprises:
counting a first number of bit errors during the first half of the first time interval;
counting a second number of bit errors during the second half of the first time interval; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the adjusting of the frequency of the local reference clock is based on the comparison.

12. The non-transitory CRM of claim 8 , further comprising instructions when executed by the processor causes the processor to:
apply, after adjusting the frequency of the local reference clock, the first set of positive dither values to the local reference clock during a first half of a second time interval;
apply, after adjusting the local reference clock, the second set of negative dither values to the local reference clock during a second half of the second time interval;
sample, during the second time interval and using the local reference clock, a second plurality of data values received over the asynchronous link, wherein the second plurality of data values are transmitted over the asynchronous link based on the remote reference clock;
count a first number of bit errors from the sampling of the second plurality of data values during the first half of the second time interval;
count a second number of bit errors from the sampling of the second plurality of data values during the second half; and
generate a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the comparison indicates that the first number of bit errors and the second number of bit errors are balanced.

13. A system for reducing a frequency error, comprising:
a local reference clock comprising a divider;
a clock and data recovery (CDR) circuit configured to sample, using the local reference clock, a plurality of data values during a first time interval, wherein

Assignees

• Barrow Shawn
• Ciena Corp

Inventors

• Barrow Shawn

Classifications

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L1/20

  using signal quality detector · CPC title

• H04L7/0054

  Detection of the synchronisation error by features other than the received signal transition (by means of signal transition H04L7/033) · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title