Protective via cap for improved interconnect performance

Patent metadata

Field	Value
Publication number	US-9847289-B2
Application number	US-201414291466-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Exemplary methods of forming a semiconductor structure may include etching a via through a semiconductor structure to expose a first circuit layer interconnect metal. The methods may include forming a layer of a material overlying the exposed first circuit layer interconnect metal. The methods may also include forming a barrier layer within the via having minimal coverage along the bottom of the via. The methods may additionally include forming a second circuit layer interconnect metal overlying the layer of material.

First claim

The invention claimed is:

1. A method of forming a semiconductor structure comprising:
etching a via through a semiconductor structure, wherein the etching exposes a first metal;
forming a layer of material overlying the exposed first metal subsequent the etching;
depositing a barrier layer within the etched via, wherein the as-deposited barrier layer is characterized by a first thickness along the sidewalls of the via, and a second thickness less than the first thickness overlying the layer of material; and
forming a second metal overlying the layer of material.

2. The method of claim 1 , wherein the layer of material comprises a transition metal or a transition metal oxide.

3. The method of claim 1 , wherein the layer of material is formed to a thickness of between about 0.5 nm and 10 nm.

4. The method of claim 1 , wherein the via includes no other materials besides the second metal and barrier materials.

5. The method of claim 4 , wherein the barrier layer comprises a transition metal.

6. The method of claim 5 , wherein the barrier layer comprises manganese.

7. The method of claim 1 , wherein at least one of the first metal and the second metal comprise copper.

8. The method of claim 1 , wherein the first metal comprises an interconnect for a first level of a semiconductor structure, and the second metal comprises an interconnect for a second level of a semiconductor structure.

9. The method of claim 1 , wherein at least a portion of the etch comprises:
contacting a portion of the semiconductor structure with non-reactive ions from a capacitively coupled plasma; and
exposing the contacted portion of the semiconductor structure to a plasma-generated reactive species.

10. The method of claim 1 , wherein the etching is performed as an operation of a single or dual damascene process.

11. The method of claim 1 , wherein the semiconductor structure is maintained under vacuum between the etching operation and the layer of material forming operation.

12. A method of forming a protective cap within an integrated circuit structure, the method comprising:
etching a via through a semiconductor structure, wherein the semiconductor structure comprises at least a first circuit layer and a second circuit layer, and wherein the etching is performed through the second circuit layer to expose an interconnect metal in the first circuit layer;
cleaning the interconnect metal;
forming a cobalt-containing protective cap overlying the exposed first metal;
forming a barrier layer comprising manganese directly contacting the sidewalls of the semiconductor structure defining the via, wherein the barrier layer is formed overlying the cobalt-containing protective cap and is characterized at the time of formation by a non-negligible thickness of less than 50% of the thickness deposited along the sidewalls of the via, and wherein the barrier layer has a thickness at the sidewalls of less than or about 10 nm; and
filling the via with copper directly overlying the barrier layer.

13. The method of claim 1 , wherein the forming a layer of material operation comprises bringing the semiconductor structure in proximity to a heating element.

14. The method of claim 13 , wherein the heating element causes sublimation of byproducts.

15. The method of claim 12 , wherein the cleaning comprises a UV clean.

16. The method of claim 12 , wherein the cleaning comprises a reactive clean utilizing an in situ hydrogen plasma.

17. The method of claim 12 , wherein the cobalt-containing protective cap is characterized by a thickness of between about 10 Å and about 40 Å.

18. The method of claim 12 , wherein forming the cobalt-containing protective cap is performed prior to etching the via, and wherein the method further comprises:
oxidizing at least a portion of the cobalt-containing protective cap after formation.

19. The method of claim 1 , wherein the layer of material overlying the exposed first metal is formed to cover the exposed first metal.

Assignees

• Applied Materials Inc

Inventors

• Naik Mehul
• Ma Paul F
• Nemani Srinivas D

Classifications

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084

  for dual-damascene structures · CPC title