Metal reflow for middle of line contacts

US9847261B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9847261-B2
Application numberUS-201615134750-A
CountryUS
Kind codeB2
Filing dateApr 21, 2016
Priority dateDec 2, 2015
Publication dateDec 19, 2017
Grant dateDec 19, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a contact in a semiconductor device, the method comprising: forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along sidewalls of the trench and a bottom portion of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of high purity cobalt that includes less than 100 parts per million of carbon on a surface of the first gate and a surface of the second gate; heating to reflow the layer of high purity cobalt on the surface of the first gate and the second gate into the trench and directly on the liner, the high purity cobalt completely filling the bottom portion of the trench and forming a thin film on upper sidewalls of the trench such that a thickness of the high purity cobalt on upper sidewalls of the trench is substantially thinner than a thickness that completely fills the bottom portion of the trench; and depositing a metal directly on the layer of high purity cobalt to fill remaining portions of the trench and form the contact; wherein the contact consists essentially of the liner, the layer of high purity cobalt, and the metal. 2. The method of claim 1 , wherein the liner is Co, Ti, CoTi, Ni, Pt, NiPt, NiPtTi, Ta, TaNi, TaAl, TaAlN, TiN, TiAl, TiAlN, or any combination thereof. 3. The method of claim 1 , wherein the PVD method is sputtering. 4. The method of claim 1 , wherein the layer of high purity cobalt has a thickness in a range from about 2 to about 100 nm. 5. The method of claim 1 , wherein heating is performed at a temperature in a range from about 200 to about 500° C. 6. The method of claim 1 , wherein depositing by a PVD method is performed in a single step. 7. The method of claim 1 , wherein depositing by a PVD method is performed at a bias in a range from about 150 to about 800 W. 8. The method of claim 1 , wherein the layer of metal is cobalt, copper, tungsten, aluminum, or a combination thereof. 9. A method of forming a contact in a semiconductor device, the method comprising: forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along sidewalls of the trench and a bottom portion of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of high purity cobalt on a surface of the first gate and a surface of the second gate, the high purity cobalt comprising less than 100 parts per million carbon; heating to reflow cobalt from the layer of high purity cobalt on the surface of the first gate and the second gate into the trench and directly on the liner, the high purity cobalt completely filling the bottom portion of the trench and forming a thin film on upper sidewalls of the trench such that a thickness of the high purity cobalt on upper sidewalls of the trench is substantially thinner than a thickness that completely fills the bottom portion of the trench; and depositing a metal directly on the layer of high purity cobalt to fill remaining portions of the trench to form the contact; wherein the contact consists essentially of the liner, the layer of high purity cobalt, and the metal. 10. The method of claim 9 , wherein the layer of cobalt comprises less than 200 ppm impurities. 11. The method of claim 9 , wherein the heating to reflow cobalt partially fills the trench without voids. 12. The method of claim 11 , further comprising depositing a different metal on the cobalt after reflow. 13. The method of claim 12 , wherein the different metal is tungsten, copper, aluminum, or a combination thereof. 14. The method of claim 9 , wherein the depositing by a PVD method is performed at a bias in a range from about 200 to about 500 W.

Assignees

Inventors

Classifications

  • the principal metal being a transition metal · CPC title

  • H10P14/44Primary

    Physical vapour deposition [PVD] · CPC title

  • Local interconnections · CPC title

  • the openings being via holes penetrating underlying conductors · CPC title

  • by forming self-aligned vias or self-aligned contact plugs · CPC title

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What does patent US9847261B2 cover?
A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwa…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P14/44. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).