Methods for forming a device having a capped through-substrate via structure

Patent metadata

Field	Value
Publication number	US-9847256-B2
Application number	US-201615369409-A
Country	US
Kind code	B2
Filing date	Dec 5, 2016
Priority date	Aug 28, 2013
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.

First claim

What is claimed is:

1. A method of forming a device with a through-substrate via (TSV) structure, comprising:
forming a source/drain region at a frontside surface of a semiconductor substrate;
forming a first dielectric layer over the source/drain region;
forming a contact plug in the first dielectric layer and electrically connected to the source/drain region;
forming a second dielectric layer over the first dielectric layer;
patterning an opening penetrating the first dielectric layer and the second dielectric layer and extending into the semiconductor substrate;
depositing an isolation layer lining a sidewall and a bottom surface of the opening;
depositing a diffusion barrier layer over the isolation layer along the sidewall and the bottom surface of the opening;
forming a conductive layer over the diffusion barrier layer to fill the opening; and
forming a capping layer comprising cobalt on a top surface of the conductive layer; and
forming a third dielectric layer over the capping layer, wherein after forming the third dielectric layer, the capping layer extends from below a top surface of the isolation layer to above the top surface of the isolation layer, and wherein the top surface of the isolation layer is substantially parallel to the frontside surface of the semiconductor substrate.

2. The method of claim 1 , wherein forming the capping layer comprises a chemical vapor deposition (CVD) process.

3. The method of claim 1 further comprising forming an etch stop layer between the first dielectric layer and the second dielectric layer.

4. The method of claim 3 , wherein the etch stop layer extends below a bottom surface of the capping layer.

5. The method of claim 1 further comprising forming a metal layer in the second dielectric layer before forming the opening.

6. The method of claim 1 further comprising forming an etch stop layer over the second dielectric layer and the capping layer, wherein the etch stop layer extends along a sidewall of the capping layer, and wherein the sidewall of the capping layer is non-parallel to the top surface of the isolation layer.

7. The method of claim 1 , wherein an end of the capping layer is substantially aligned with an interface between the diffusion barrier layer and the isolation layer and not aligned with an interface between the isolation layer and the semiconductor substrate.

8. A method comprising:
depositing a first dielectric layer over a semiconductor substrate;
patterning an opening extending through the first dielectric layer into the semiconductor substrate;
depositing an isolation layer along a sidewall and a bottom surface of the opening;
depositing a diffusion barrier over the isolation layer along the sidewall and the bottom surface of the opening;
forming a conductive layer over the diffusion barrier;
forming a cobalt-comprising capping layer over a top surface of the conductive layer, wherein a top surface of the isolation layer intersects a sidewall of the cobalt-comprising capping layer, wherein the top surface of the isolation layer is substantially parallel to a major surface of the semiconductor substrate, and wherein the sidewall of the cobalt-comprising capping layer is substantially perpendicular to the major surface of the semiconductor substrate; and
depositing a second dielectric layer over and extending along the sidewall of the cobalt-comprising capping layer.

9. The method of claim 8 , wherein a lateral dimension of the cobalt-comprising capping layer is substantially equal to a lateral dimension measured from a first interface between the diffusion barrier and the isolation layer to a second interface between the diffusion barrier and the isolation layer, and wherein the lateral dimension of the cobalt-comprising capping layer is less than a lateral dimension measured from a first interface between the isolation layer and the semiconductor substrate to a second interface between the isolation layer and the semiconductor substrate.

10. The method of claim 8 further, wherein the second dielectric layer is an etch stop layer.

11. The method of claim 8 further comprising:
depositing a third dielectric layer over the first dielectric layer; and forming a conductive feature in the third dielectric layer, wherein patterning the opening comprises patterning the opening through the third dielectric layer adjacent the conductive feature.

12. The method of claim 11 , wherein forming the conductive feature comprises forming the conductive feature prior to patterning the opening.

13. The method of claim 11 , wherein the conductive feature is electrically connected to a source/drain region formed at a top surface of the semiconductor substrate.

14. The method of claim 11 , wherein forming the cobalt-comprising capping layer comprises an electroless plating process or an immersion plating process.

15. The method of claim 8 , wherein depositing the first dielectric layer comprises depositing the first dielectric layer around a gate electrode of a transistor.

16. A method of forming a device with a through-substrate via (TSV) structure, comprising:
depositing a first dielectric layer over a frontside of a semiconductor substrate, wherein a source/drain region is disposed on the frontside of the semiconductor substrate;
forming a contact plug extending through the first dielectric layer and electrically connected to the source/drain region;
forming a second dielectric layer over the first dielectric layer and the contact plug;
forming an opening extending through the second dielectric layer into the semiconductor substrate;
depositing an isolation layer along a sidewall of the opening;
depositing a diffusion barrier layer over the isolation layer and along the sidewall of the opening;
filling a remaining portion of the opening with a conductive layer;
forming a capping layer over a top surface of the conductive layer and the diffusion barrier layer, wherein the isolation layer extends along a sidewall of the capping layer, and wherein the sidewall of the capping layer is substantially perpendicular to a major surface of the semiconductor substrate; and
depositing an etch-stop layer over and extending along the sidewall of the capping layer.

17. The method of claim 16 , wherein forming the capping layer comprises a chemical vapor deposition (CVD) process, an electroless plating process, or an immersion plating process.

18. The method of claim 16 , wherein the capping layer comprises cobalt.

19. The method of claim 16 further comprising forming a conductive feature over and electrically connected to the conductive layer, wherein the conductive feature forms an interface with a top surface of the capping layer, and wherein the top surface of the capping layer is substantially parallel to the major surface of the semiconductor substrate.

20. The method of claim 16 further comprising forming a conductive feature over and electrically connected to the conductive layer, wherein the conductive feature extends through the capping layer to the conductive layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yung-Chi
• Chen Yen-Hung
• Chen Yin-Hua
• Liao Ebin
• Yang Ku-Feng
• Wu Tsang-Jiuh
• Chiou Wen-Chih

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title