Method and apparatus for using universal cavity wafer in wafer level packaging

US9847230B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9847230-B2
Application numberUS-201615177723-A
CountryUS
Kind codeB2
Filing dateJun 9, 2016
Priority dateJun 9, 2015
Publication dateDec 19, 2017
Grant dateDec 19, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming an electronics module assembly, the method comprising: creating a cavity wafer by etching a wafer to form a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports; placing at least one group of dies in the single frontside cavity; and flowing encapsulant from a backside of the cavity wafer through the fillports and into the single frontside cavity to surround the at least one group of dies. 2. The method of claim 1 , further comprising etching a single backside cavity in the cavity wafer. 3. The method of claim 1 , further comprising applying heat to the electronics module assembly to cure the encapsulant; and removing excess encapsulant to the point that the encapsulant fills the backside cavity. 4. The method of claim 1 , further comprising removing a backside of the cavity wafer to expose the fillports. 5. The method of claim 4 , further comprising: applying heat to the electronics module assembly to cure the encapsulant; and removing excess encapsulant from the backside of the cavity wafer to form a uniform layer of the encapsulant on the backside of the cavity wafer. 6. The method of claim 5 , wherein a thickness of the layer of encapsulant on the backside of the cavity wafer is determined to reduce bowing from encapsulant in the frontside cavity. 7. The method of claim 5 , further comprising: removing the layer of encapsulant on the backside of the cavity wafer to reduce bowing from the encapsulant in the frontside cavity. 8. The method of claim 7 , further comprising: removing a portion of the cavity wafer at the backside with a uniform thickness to further reduce bowing from the encapsulant in the frontside cavity.

Assignees

Inventors

Classifications

  • B81B7/0077Primary

    Other packages not provided for in groups B81B7/0035 - B81B7/0074 · CPC title

  • Protect against mechanical threats, e.g. against shocks, or residues (B81C1/00261 take precedence) · CPC title

  • Moulding a cap over the MEMS device · CPC title

  • on encapsulations · CPC title

  • On different surfaces · CPC title

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Frequently asked questions

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What does patent US9847230B2 cover?
An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also includ…
Who is the assignee on this patent?
Charles Stark Draper Laboratory Inc
What technology area does this patent fall under?
Primary CPC classification B81B7/0077. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Dec 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).