Utilization of solid state memory devices

Patent metadata

Field	Value
Publication number	US-9846661-B2
Application number	US-201414333943-A
Country	US
Kind code	B2
Filing date	Jul 17, 2014
Priority date	Jul 17, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Technologies are generally described for systems, devices and methods effective to utilize a solid state memory device. A memory device may include one or more input/output ports effective to receive data at, and facilitate transfer from, the memory device. The memory device may further include a memory controller. The memory controller may be effective to control access to data stored in the memory device. The memory device may further include two or more flash chips effective to store data in the memory device. The memory device may further include a crossbar switch. The crossbar switch may be coupled between the one or more input/output ports and the two or more flash chips. The crossbar switch may be effective to enable the one or more input/output ports to access the two or more flash chips through the memory controller.

First claim

What is claimed is:

1. A memory device, comprising:
one or more input/output ports configured to receive data at the memory device and facilitate transfer of data from the memory device;
a memory controller configured to control access to data stored in the memory device, wherein the memory controller includes a solid state device controller configured to be in communication with a flash controller;
at least one flash memory chip configured to store data in the memory device; and
a crossbar switch coupled between the solid state device controller and the flash controller, wherein the crossbar switch is configured to allow the one or more input/output ports to access the at least one flash memory chip through the memory controller.

2. The memory device of claim 1 , wherein the crossbar switch includes a plurality of transistors, wherein each transistor is effective to couple a particular output to a particular input.

3. The memory device of claim 1 , further comprising another crossbar switch coupled between the flash controller and the at least one flash memory chip.

4. The memory device of claim 1 , further comprising another crossbar switch coupled between the solid state device controller and the one or more input/output ports.

5. The memory device of claim 4 , further comprising still another crossbar switch coupled between the flash controller and the at least one flash memory chip.

6. A method to operate a memory device, wherein the memory device includes a first flash memory chip and a second flash memory chip, the method comprising:
establishing communication between the first flash memory chip and a first data server;
establishing communication between the second flash memory chip and the first data server; and
switching communication of the first flash memory chip from the first data server to a second data server while maintaining communication between the second flash memory chip and the first data server.

7. The method of claim 6 , wherein switching is based on a policy of the first data server, and wherein the policy specifies a percentage of flash memory chips allocated to the first data server.

8. The method of claim 6 , wherein switching is based on a policy of the first data server, and wherein the policy relates to an amount of direct attached storage usable by the first data server.

9. The method of claim 6 , wherein switching is based on a policy of the first data server, and wherein the policy relates to an amount of network attached storage usable by the first data server.

10. The method of claim 6 , wherein the memory device further includes:
a solid state device controller configured to be in communication with an input/output port; and
a flash controller configured to be in communication with the solid state device controller and the first and second flash memory chips, wherein:
switching communication includes using a crossbar switch configured between the solid state device controller and the flash controller to perform the switching communication.

11. The method of claim 6 , wherein the memory device further includes:
a flash controller configured to be in communication with the first and second flash memory chips, wherein:
switching communication includes using a crossbar switch configured between the flash controller and the first and second flash memory chips to perform the switching communication.

12. The method of claim 6 , wherein the memory device further includes:
a solid state device controller configured to be in communication with an input/output port, wherein:
switching communication includes using a crossbar switch configured between the solid state device controller and the input/output port to perform the switching communication.

13. The method of claim 6 , wherein the memory device further includes:
a solid state device controller configured to be in communication with an input/output port; and
a flash controller configured to be in communication with the solid state device controller and the first and second flash memory chips, wherein:
switching communication includes using, a first crossbar switch configured between the solid state device controller and the flash controller and a second crossbar switch configured between the flash controller and the first and second flash memory chips, to perform the switching communication.

14. The method of claim 6 , wherein the memory device further includes:
a solid state device controller configured to be in communication with an input/output port; and
a flash controller configured to be in communication with the solid state device controller and the first and second flash memory chips, wherein:
switching communication includes using, a first crossbar switch configured between the solid state device controller and the flash controller, a second crossbar switch configured between the flash controller and the first and second flash memory chips, and a third crossbar switch configured between the input/output port and the solid state device controller, to perform the switching communication.

15. A method to operate a memory device, the method comprising:
determining, by a memory controller of a solid state storage device, that a processor element of the memory controller is performing an operation other than a data storage operation for the solid state storage device;
based on the determination, retrieving, by the memory controller, a mission that relates to processing of data in one or more flash memory chips of the solid state storage device that are accessible by the processor element; and
executing the mission by the processor element.

16. The method of claim 15 , wherein determining that the processor element of the memory controller is performing the operation other than the data storage operation comprises determining that the memory controller is not performing the data storage operation during a time frame between read/write operations of the solid state storage device.

17. The method of claim 15 , further comprising:
suspending execution of the mission by the processor element in response to receipt of a new data storage operation by the memory controller; and
executing the new data storage operation by the memory controller.

18. The method of claim 17 , further comprising resuming the execution of the mission after the execution of the new data storage operation has completed.

19. The method of claim 15 , wherein retrieving the mission by the memory controller includes retrieving the mission by one of a solid state device controller and a flash controller.

20. A memory system, comprising:
a solid state storage device;
a first data server configured to be in communication with the solid state storage device; and
a second data server configured to be in communication with the solid state storage device and the first data server,
wherein the solid state storage device comprises:
one or more input/output ports configured to receive data at the solid state storage device and facilitate transfer of data from the solid state storage device;
a memory controller;
a first flash memory chip and a second flash memory chip configured to store data received through the one or more input/output ports in the solid state storage device; and
a crossbar switch,

wherein the memory controller is configured to:
control access to data stored in the solid state storage device; and
control operation of the crossbar switch; and

wherein the crossbar switch is configured to:
establish communicatio

Assignees

• Empire Technology Dev Llc

Inventors

• Margalit Mordehai
• Ur Shmuel
• Hirshberg David
• Gruper Shimon
• Kaplan Menahem

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title