Memory access scheme for system on chip

Patent metadata

Field	Value
Publication number	US-9292380-B2
Application number	US-201414246140-A
Country	US
Kind code	B2
Filing date	Apr 6, 2014
Priority date	Apr 6, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.

First claim

The invention claimed is:

1. A method of processing data within an integrated circuit, the method comprising:
(a) processing a first set of data using a first hardware processor to generate a second set of data;
(b) storing the second set of data in a first memory;
(c) remapping addresses of the first memory with addresses of a second memory to swap the first and second memories; and
(d) accessing and processing the second set of data in the first memory by a second hardware processor using the remapped addresses of the first memory to generate a third set of data.

2. The method of claim 1 , wherein step (d) further comprises storing the third set of data into the first memory.

3. The method of claim 1 , wherein the second memory is a tightly coupled memory for the second hardware processor.

4. The method of claim 1 , wherein the first memory is part of system memory that can be accessed by the first and second hardware processors via a data crossbar switch.

5. The method of claim 4 , wherein step (d) comprises the second hardware processor bypassing the data crossbar switch to access the second set of data in the first memory.

6. The method of claim 5 , wherein the second memory is a tightly coupled memory for the second hardware processor.

7. The method of claim 1 , wherein:
the first memory stores second error correction code (ECC) data for the second set of data and second ECC address information linking the second ECC data to the second set of data; and
step (d) further comprises accessing the second ECC data and the second ECC address information in the first memory and remapping the second ECC address information on the fly.

8. The method of claim 7 , wherein step (d) further comprises storing, into the first memory, the third set of data, third ECC data for the third set of data, and third ECC address information linking the third ECC data to the third set of data.

9. The method of claim 8 , wherein the third ECC address information is remapped dynamically.

10. An integrated circuit, comprising:
a first hardware processor;
a first memory associated with the first hardware processor;
a second hardware processor; and
a second memory associated with the second hardware processor, wherein:
the first hardware processor is configured to (i) process a first set of data to generate a second set of data and (ii) store the second set of data in the first memory; and
the second hardware processor is configured to (i) remap addresses of the first memory with addresses of the second memory to swap the first and second memories and (ii) access and process the second set of data in the first memory using the remapped addresses of the first memory to generate a third set of data.

11. The integrated circuit of claim 10 , wherein the second hardware processor is configured to store the third set of data into the first memory.

12. The integrated circuit of claim 10 , wherein the second memory is a tightly coupled memory for the second hardware processor.

13. The integrated circuit of claim 10 , wherein the first memory is part of system memory that can be accessed by the first and second hardware processors via a data crossbar switch of the integrated circuit.

14. The integrated circuit of claim 13 , wherein the second hardware processor is configured to bypass the data crossbar switch to access the second set of data in the first memory.

15. The integrated circuit of claim 14 , wherein the second memory is a tightly coupled memory for the second hardware processor.

16. The integrated circuit of claim 10 , wherein:
the first memory is configured to store second ECC data for the second set of data and second ECC address information linking the second ECC data to the second set of data; and
the second hardware processor is configured to (i) access the second ECC data and the second ECC address information in the first memory and (ii) remap the second ECC address information dynamically.

17. The integrated circuit of claim 16 , wherein the second hardware processor is configured to store, into the first memory, the third set of data, third ECC data for the third set of data, and third ECC address information linking the third ECC data to the third set of data.

18. The integrated circuit of claim 17 , wherein the second hardware processor is configured to remap the third ECC address information dynamically.

Assignees

• Singh Nitin
• Jain Gaurav
• Jindal Amit
• Tomar Rohit
• Freescale Semiconductor Inc

Inventors

• Singh Nitin
• Jain Gaurav
• Jindal Amit
• Tomar Rohit

Classifications

• G06F11/165

  with continued operation after detection of the error · CPC title

• G06F11/1412

  Physics · mapped topic

• G06F12/063

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• G06F2212/206

  Memory mapped I/O · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title