Semiconductor device with different fin sets

Patent metadata

Field	Value
Publication number	US-2016197072-A1
Application number	US-201615073100-A
Country	US
Kind code	A1
Filing date	Mar 17, 2016
Priority date	May 19, 2014
Publication date	Jul 7, 2016
Grant date	—

Abstract

A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

First claim

That which is claimed is:

1 . A semiconductor device comprising:
a substrate; a first set of fins above the substrate comprising a first semiconductor material; a second set of fins above the substrate and comprising a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer.

2 . The semiconductor device of claim 1 wherein the isolation region comprises an isolation pillar extending above the substrate and positioned between the first and second sets of fins.

3 . The semiconductor device of claim 2 wherein at least a portion of the isolation pillar extends into the substrate.

4 . The semiconductor device of claim 2 wherein the isolation pillar is spaced apart from the first and second sets of fins.

5 . The semiconductor device of claim 2 wherein the isolation pillar is in contact with at least one fin from the first and second sets of fins.

6 . The semiconductor device of claim 1 wherein the isolation region comprises an isolation trench positioned between the first and second sets of fins, and the nitride liner is in the isolation trench.

7 . The semiconductor device of claim 6 wherein the isolation trench extends into the substate.

8 . The semiconductor device of claim 1 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon germanium.

9 . The semiconductor device of claim 1 further comprising:
at least one gate overlying the first and second sets of fins; and
respective source and drain regions electrically coupled with each of the first and second sets of fins.

10 . A semiconductor device comprising:
a substrate; a first set of fins above the substrate comprising a first semiconductor material; a second set of fins above the substrate and comprising a second semiconductor material different than the first semiconductor material; and an isolation pillar extending above the substrate and positioned between the first and second sets of fins, the isolation pillar comprising an inner oxide portion, a nitride layer on the inner oxide portion, and an outer oxide layer on the nitride layer.

11 . The semiconductor device of claim 10 wherein at least a portion of the isolation pillar extends into the substrate.

12 . The semiconductor device of claim 10 wherein the isolation pillar is spaced apart from the first and second sets of fins.

13 . The semiconductor device of claim 10 wherein the isolation pillar is in contact with at least one fin from the first and second sets of fins.

14 . The semiconductor device of claim 10 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon germanium.

15 . The semiconductor device of claim 10 further comprising:
at least one gate overlying the first and second sets of fins; and
respective source and drain regions electrically coupled with each of the first and second sets of fins.

16 . A semiconductor device comprising:
a substrate; a first set of fins above the substrate comprising a first semiconductor material; and a second set of fins above the substrate and comprising a second semiconductor material different than the first semiconductor material; the substrate having an isolation trench positioned between the first and second sets of fins, and a nitride liner in the isolation trench.

17 . The semiconductor device of claim 16 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon germanium.

18 . The semiconductor device of claim 16 further comprising:
at least one gate overlying the first and second sets of fins; and
respective source and drain regions electrically coupled with each of the first and second sets of fins.

19 . The semiconductor device of claim 16 wherein at least a portion of the isolation trench extends into the substrate.

20 . The semiconductor device of claim 16 wherein the isolation trench is spaced apart from the first and second sets of fins.

Assignees

• IBM
• St Microelectronics Inc
• Globalfoundries Inc

Inventors

• Liu Qing
• Cai Xiuyu
• Xie Ruilong
• Yeh Chun-Chen
• Wang Kejia
• Chanemougame Daniel

Classifications

• H10D86/215 Primary

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title