Semiconductor device, finfet transistor and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016351591-A1
Application number	US-201615169818-A
Country	US
Kind code	A1
Filing date	Jun 1, 2016
Priority date	Jun 1, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate having a surface; forming at least one fin over the surface of the semiconductor substrate; forming a mask layer on side surfaces of the fin; forming insulation layer trenches in the semiconductor substrate by etching the semiconductor substrate using the mask layer as an etching mask; forming silicon oxide layers on side surfaces of the insulation layer trenches under the fins; forming first nitrogen-doped oxide layers by doping nitrogen into the silicon oxide layers; and filling the insulation layer trenches with nitrogen-doped silicon oxide to form second nitrogen-doped silicon oxide layers, the first nitrogen-doped silicon oxide layers and the second nitrogen-doped silicon oxide layer form an insulation layer under the fin.

2 . The method according to claim 1 , wherein:
the silicon oxide layers are formed by an oxidation process.

3 . The method according to claim 2 , wherein:
a reaction gas of the oxidation process is oxygen; a temperature of the oxidation process is in a range of approximately 100° C.-1000° C.; a flow rate of the reaction gas is in a range of approximately 20 sccm-2000 sccm; a pressure of the oxidation process is in a range of approximately 0.01 Torr-50 Torr; and a power of the oxidation process is in a range of approximately 50 W-10000 W.

4 . The method according to claim 1 , wherein forming the insulation layer trenches comprises:
forming first trenches in the semiconductor substrate by etching the semiconductor substrate using the mask layer as an etching mask; and extending side surfaces of the first trenches under the fin.

5 . The method according to claim 4 , wherein:
the first trenches are formed by a dry etching process; and the side surfaces of the first trenches are extended by a wet etching process.

6 . The method according to claim 5 , wherein:
an etching gas of the dry etching process includes one of CF 4 and NF 3 ; a flow rate of the etching gas is in a range of approximately 10 sccm-2000 sccm; a pressure of the dry etching process is in a range of approximately 0.01 mTorr-50 mTorr; and a power of the dry etching process is in a range of approximately 50 W-10000 W.

7 . The method according to claim 5 , wherein:
an etching solution of the wet etching process is a diluted HF solution; and a volume ratio of HF and water in the diluted HF solution is in a range of approximately 1:300-1:1000.

8 . The method according to claim 1 , wherein forming the first nitrogen-doped layers comprises:
generating a nitrogen plasma to treat the silicon oxide layers, and doping nitrogen into the silicon oxide layers.

9 . The method according to claim 8 , wherein generating the nitrogen plasma comprises:
introducing one of N 2 , NH 3 and N 2 H 2 into a plasma generator.

10 . The method according to claim 9 , wherein:
a flow rate of one of N 2 , NH 3 and N 2 H 2 is in a range of approximately 20 sccm-2000 sccm; a pressure in the plasma generator is in a range of approximately 0.01 Torr-50 Torr; and a power of the plasma generator is in a range of approximately 50 W-10000 W.

11 . The method according to claim 1 , before filling the nitrogen-doped oxide into the insulation layer trenches, further comprising:
removing the mask layer.

12 . The method according to claim 11 , wherein:
the mask layer is made of silicon nitride; and the mask layer is removed by a wet etching process using phosphoric acid as an etching solution.

13 . The method according to claim 11 , wherein:
a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.

14 . A method for fabricating a fin field-effect transistor according to claim 1 , further comprising:
forming a gate structure crossing over the fin, and covering top and side surfaces of the fin over the semiconductor substrate; and forming a source in the fin at one side of the gate structure and a drain in the fin at another side of the gate structure.

15 . A semiconductor device, comprising:
a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the semiconductor device formed over the semiconductor substrate; and at least one fin formed over the insulation layer.

16 . The semiconductor device according to claim 15 , wherein:
the insulation layer is made of nitrogen-doped silicon oxide.

17 . The semiconductor device according to claim 15 , wherein:
a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.

18 . A fin field-effect transistor, comprising:
a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin-field effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the first fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

19 . The fin field-effect transistor according to claim 18 , wherein:
the insulation layer is made of nitrogen-doped silicon oxide.

20 . The fin field-effect transistor according to claim 18 , wherein:
a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xie Xinyun
• Zhou Ming

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title