High density interconnection of microelectronic devices

Patent metadata

Field	Value
Publication number	US-9842832-B2
Application number	US-201615183179-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Dec 11, 2013
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

First claim

What is claimed is:

1. A microelectronic package comprising:
a first microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;
a second microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;
wherein the at least one side of the first microelectronic device abuts the at least one side of the second microelectronic device, and wherein at least one connection structure within the at least one first microelectronic device row is aligned with a corresponding connection structure within the at least one second microelectronic device row in an x-direction; and
an interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate, wherein the interconnect is attached to the at least one first microelectronic device connection structure row and at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

2. The microelectronic package of claim 1 , wherein the interconnect substrate comprises a silicon.

3. The microelectronic package of claim 1 , wherein the interconnect substrate comprises a flexible material.

4. The microelectronic package of claim 1 , wherein the interconnect conductive traces have a trace pitch of 5 μm or less.

5. The microelectronic package of claim 1 , further comprising a carrier, wherein the back surface of the first microelectronic device and the back surface of the second microelectronic device are attached to the carrier.

6. A microelectronic package comprising:
a first microelectronic device having an active surface and an opposing back surface;
a second microelectronic device having an active surface and an opposing back surface;
a connection trace network formed over the first microelectronic device and the second microelectronic device, wherein the connection trace network has at least one row of connection structures formed in or on the connection trace network which are electrically connected the first microelectronic device and at least one other row of connection structures formed in or on the connection trace network which are electrically connected the second microelectronic device, and wherein at least one connection structure within the at least one row connect to the first microelectronic device is aligned with a corresponding connection structure within the at least one other row of connection structure connected to the second microelectronic device row in an x-direction; and
an interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate, wherein the interconnect is attached to the at least one first microelectronic device connection structure row and at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure, and wherein the interconnect conductive traces have a trace pitch of 5 μm or less.

7. The microelectronic package of claim 6 , wherein the interconnect substrate comprises a silicon.

8. The microelectronic package of claim 6 , wherein the interconnect substrate comprises a flexible material.

9. The microelectronic package of claim 6 , further comprising a carrier, wherein the back surface of the first microelectronic device and the back surface of the second microelectronic device are attached to the carrier.

10. The microelectronic package of claim 6 , further comprising a cavity within the connection trace network, wherein the first microelectronic device row of connection structures and the second microelectronic device row of connection structures are formed within the connection trace network cavity.

11. A computing device, comprising:
a board; and
at least one of a processor and a communication chip electrically coupled to the board wherein the at least one of a processor and a communication chip comprises a microelectronic package including:
a first microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;
a second microelectronic device having an active surface, an opposing back surface, at least one side, and at least one row of connection structures formed on the active surface;
wherein the at least one side of the first microelectronic device abuts the at least one side of the second microelectronic device, and wherein at least one connection structure within the at least one first microelectronic device row is aligned with a corresponding connection structure within the at least one second microelectronic device row in an x-direction; and
an interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate, wherein the interconnect is attached to the at least one first microelectronic device connection structure row and at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

12. The computing device of claim 11 , wherein the interconnect substrate comprises a silicon.

13. The computing device of claim 11 , wherein the interconnect substrate comprises a flexible material.

14. The computing device of claim 11 , wherein the interconnect conductive traces have a trace pitch of 5 μm or less.

15. The computing device of claim 11 , further comprising a carrier, wherein the back surface of the first microelectronic device and the back surface of the second microelectronic device are attached to the carrier.

16. A computing device, comprising:
a board; and
at least one of a processor and a communication chip electrically coupled to the board wherein the at least one of a processor and a communication chip comprises a microelectronic package including:
a first microelectronic device having an active surface and an opposing back surface;
a second microelectronic device having an active surface and an opposing back surface;
a connection trace network formed over the first microelectronic device and the second microelectronic device, wherein the connection trace network has at least one row of connection structures formed in or on the connection trace network which are electrically connected the first microelectronic device and at least one other row of connection structures formed in or on the connection trace network which are electrically connected the second microelectronic device, and wherein at least one connection structure within the at least one row connect to the first microelectronic device is aligned with a corresponding connection structure within the at least one other row of connection structure connected to the second microelectronic device row in an x-direction; and
an interconnect comprising an i

Assignees

• Intel Corp

Inventors

• Karhade Omkar G
• Guzek John S
• Swan Johanna M
• Nelson Christopher J
• Deshpande Nitin A
• Lambert William J
• Gealer Charles A
• Eid Feras
• Salama Islam A
• Aygun Kemal
• Oster Sasha N
• Osborn Tyler N

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9413

  on encapsulations · CPC title