Method, apparatus and system for using hybrid library track design for SOI technology

Patent metadata

Field	Value
Publication number	US-9842184-B2
Application number	US-201615047878-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Sep 11, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

First claim

What is claimed is:

1. A method, comprising:
placing a first functional cell having a first width on a circuit layout;
determining whether at least one transistor of said first functional cell is to be forward biased or reversed biased;
placing a second functional cell having a second width adjacent to said first functional cell on said circuit layout for providing a first biasing well within the total width of said first and second functional cells in response to determining that said at least one transistor is to be forward biased or reversed biased;
placing a third functional cell having said first width adjacent said second functional cell;
placing a fourth functional cell having said second width adjacent said third functional cell for providing a second biasing well within the total width of said first, second, third, and fourth functional cells; and
processing a semiconductor wafer for forming a device comprising said first and second functional cells.

2. The method of claim 1 , wherein:
placing said first functional cell having a first width on a circuit layout comprises placing an m-track cell, wherein m is equal to at least one of 9, 10, or 11;
placing said second functional cell having a second width comprises placing at least one of an (m−1)-track cell or an (m−2) cell.

3. The method of claim 1 , wherein providing said first biasing well comprises providing an isolation region between said first functional cell and said second functional cell.

4. The method of claim 1 , wherein providing said first biasing well within the total width of said first and second functional cells comprises arranging said first functional cell, said second functional cell, and said biasing well within two times the first width.

5. The method of claim 1 , further comprising routing a first biasing voltage signal in said first biasing well.

6. The method of claim 1 , wherein placing said first, second, third, and fourth functional cells comprises placing cells comprising at least one of FD SOI LVT transistors, FD SOI SLVT transistors, FD SOI RVT transistors, or FD SOI HVT transistors.

7. A method, comprising:
providing a device design comprising a hybrid functional cell block, wherein said hybrid functional cell block comprising a first device type cell and a second device type cell, wherein providing said device design comprises:
placing a first functional cell of said first device type in a circuit layout, wherein said first functional cell has a first width;
placing a second functional cell of said second device type adjacent said first functional cell, said second functional cell having a second width for providing an isolation channel between said first and second functional cells;
determining whether an isolation spacing should be formed for at least one of providing a biasing channel or creating an isolation channel for adjacently placing functional cells of different device types;
determining a size of at least one of said biasing channel or said isolation channel based on determining that said isolation spacing should be formed; and
determining the track width size of the second functional cell based upon said size; and

processing a semiconductor wafer for forming a device comprising said first and second functional cells.

8. The method of claim 7 , wherein:
placing said first functional cell having a first width on said circuit layout comprises placing at least one of a 9-track cell, a 10-track cell, or a 11-track cell;
placing said second functional cell having a second width comprises placing a cell that has a second width of one track smaller than said first width, or two tracks smaller than said first width.

9. The method of claim 7 , further comprising performing an operation modeling of said device design for determining whether said device design comprises at least one of a timing error or a performance error.

10. The method of claim 9 , wherein performing said operation modeling comprises at least one of testing for timing errors, determining a design change for reducing timing errors, or determining a design change for improving a performance of said semiconductor device circuit design.

11. The method of claim 9 , further comprising at least one of:
identifying a circuit area in which an operation speed is be increased or decreased; or
identifying a circuit area in which a functionality can be restored to at least one of a pre-silicon tuning or a post-silicon tuning at a wider operating condition.

12. The method of claim 7 , further comprising forming said biasing channel adjacent said circuit area.

13. A semiconductor device, comprising:
a first functional cell having a first width;
a second functional cell having a second width adjacent to said first functional cell on said circuit layout for providing a first biasing well within the total width of said first and second functional cells;
a first biasing signal wire positioned in said first biasing well for providing at least one of forward biasing signal or a reverse biasing signal to at least one of said first functional cell or said second functional cell; and
a hybrid functional cell block, wherein said hybrid functional cell block comprising a first device type cell and a second device type cell, and wherein said hybrid functional cell block comprising a first functional cell of said first device type and a second functional cell of said second device type adjacent said first functional cell, said second functional cell having a second width for providing an isolation channel between said first and second functional cells within a dimension that is twice the first width.

14. The semiconductor device of claim 13 , wherein said first and second functional cells is comprised of at least one of FD SOI transistors, FD SOI LVT transistors, FD SOI SLVT transistors, FD SOI RVT transistors, or FD SOI HVT transistors.

15. The semiconductor device of claim 13 , wherein said biasing signal wire provides a signal for adjusting the operation timing of said at least a portion of said first functional cell or said second functional cell.

16. The semiconductor device of claim 13 , further comprising
a processor;
a memory device;
an interface circuit for operatively coupled to said processor and said memory device, said interface circuit comprising said first biasing signal wire, said first functional cell, and second functional cell.

Assignees

• Globalfoundries Inc

Inventors

• Mittal Anurag
• Rashed Mahbub

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title