Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit

Patent metadata

Field	Value
Publication number	US-2016321389-A1
Application number	US-201514697709-A
Country	US
Kind code	A1
Filing date	Apr 28, 2015
Priority date	Apr 28, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row. Constraint data is specified identifying a subset of the standard cells that are allowed to be placed in each body biased row, and the layout is then generated by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row, and the constraint data for each body biased row. This enables a significant improvement in the benefits that can be achieved through the use of body biasing mechanisms, for example allowing a significant increase in switching speed of the circuit block to be achieved, without a significant increase in leakage current.

First claim

I claim:

1 . A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:
receiving input data identifying a plurality of circuit elements and interconnections required to implement the circuit block; accessing a cell library providing a plurality of standard cells, each standard cell defining a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors; forming a plurality of rows within which to place standard cells from the cell library in order to implement the circuit block, said plurality of rows including at least one body biased row in which a body bias is to be applied in respect of one type of the n-type transistors and the p-type transistors provided by the standard cells placed in that body biased row; specifying constraint data identifying a subset of the standard cells that are allowed to be placed in each body biased row; and generating said layout by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row and the constraint data for each body biased row.

2 . A method as claimed in claim 1 , wherein said constraint data identifies as said subset of standard cells at least one standard cell that includes a series of transistors of said one type that are arranged in a stacked arrangement within the standard cell.

3 . A method as claimed in claim 1 , wherein said constraint data identifies as said subset of standard cells at least one standard cell used as a circuit element within a clock distribution tree used to propagate a clock signal.

4 . A method as claimed in claim 1 , wherein said body bias to be applied within each body biased row is a forward body bias.

5 . A method as claimed in claim 1 , wherein said at least one body biased row comprises a p-type body biased row in which a body bias is to be applied in respect of the p-type transistors provided by standard cells placed in that p-type body biased row, and no body bias is to be applied in respect of the n-type transistors provided by standard cells placed in that p-type body biased row.

6 . A method as claimed in claim 5 , wherein said subset of the standard cells identified by said constraint data comprises at least one standard cell that includes a series of p-type transistors that are arranged in a stacked arrangement within that standard cell.

7 . A method as claimed in claim 5 , wherein said body bias is to be applied by providing a reference voltage level to a body connection of the p-type transistors within the p-type body biased row.

8 . A method as claimed in claim 1 , wherein said at least one body biased row comprises an n-type body biased row in which a body bias is to be applied in respect of the n-type transistors provided by standard cells placed in that n-type body biased row, and no body bias is to be applied in respect of the p-type transistors provided by standard cells placed in that n-type body biased row.

9 . A method as claimed in claim 8 , wherein said subset of the standard cells identified by said constraint data comprises at least one standard cell that includes a series of n-type transistors that are arranged in a stacked arrangement within that standard cell.

10 . A method as claimed in claim 8 , wherein said body bias is to be applied by providing a supply voltage level to a body connection of the n-type transistors within the n-type body biased row.

11 . A method as claimed in claim 1 , wherein the input data identifies for each circuit element the standard cell within the standard cell library to be used for that circuit element.

12 . A method as claimed in claim 11 , wherein said constraint data is specified within the standard cell library by provision of one or more standard cells that are constrained to be used in said at least one body biased row.

13 . A method as claimed in claim 1 , wherein the constraint data is specified by user input.

14 . A method as claimed in claim 1 , wherein the constraint data identifies that all instances of the subset of standard cells must be placed within said at least one body biased row.

15 . A method as claimed in claim 1 , wherein said step of forming a plurality of rows within which to place standard cells from the cell library in order to implement the circuit block comprises:
repeating in a regular pattern a multiple of two p-type body biased rows and a multiple of two n-type body biased rows separated by one or more non-biased rows.

16 . A method as claimed in claim 1 , further comprising the steps of:
incorporating the layout of the circuit block within a layout of an integrated circuit; and manufacturing the integrated circuit from the layout of the integrated circuit.

17 . A method as claimed in claim 1 , further comprising associating configuration circuitry with said at least one body biased row to enable application of the body bias to be disabled in response to at least one predetermined condition.

18 . A method as claimed in claim 17 , wherein said at least one predetermined condition comprises one of an operating voltage exceeding a predetermined level and a power gating operation being applied to said at least one circuit block.

19 . A computer program product on a non-transitory storage medium for controlling a computer to perform a method of generating a layout of a circuit block as claimed in claim 1 .

20 . A non-transitory storage medium storing a cell library comprising a plurality of standard cells, each standard cell defining a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors, the standard cell library including at least one standard cell constrained to be used in a body biased row of a plurality of rows to be populated with standard cells from the cell library in order to implement a circuit block, the body biased row being a row in which a body bias is to be applied in respect of one type of the n-type transistors and the p-type transistors provided by standard cells placed in that body biased row.

21 . An integrated circuit comprising:
at least one circuit block comprising a plurality of circuit elements formed from standard cells of a cell library and positioned within a plurality of rows, the circuit elements comprising p-type transistors and n-type transistors; said plurality of rows including at least one body biased row in which a body bias is applied in respect of one type of the n-type transistors and the p-type transistors provided by the circuit elements positioned in that body biased row; and each body biased row containing only circuit elements formed from standard cells within a subset of the standard cells that are constrained to be placed in that body biased row.

22 . An integrated circuit as claimed in claim 21 , further comprising configuration circuitry responsive to at least one predetermined condition to disable the body bias applied to said at least one body biased row.

23 . An integrated circuit as claimed in claim 22 , wherein said at least one predetermined condition comprises one of an operating voltage exceeding a predetermined level and a power gating operation being applied to said at least one circuit block.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Myers James Edward

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H01L27/092

  Electricity · mapped topic