Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9837530-B2
Application number	US-201514868857-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 30, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

First claim

What is claimed is:

1. A semiconductor device comprising a semiconductor body, the semiconductor body comprising insulated gate field effect transistor cells, at least one of the insulated gate field effect transistor cells comprising
a source zone of a first conductivity type,
a body zone of a second, complementary conductivity type,
a drift zone of the first conductivity type, and
a trench gate structure extending into the semiconductor body through the body zone along a vertical direction and comprising a gate electrode separated from the semiconductor body by a trench dielectric, the trench dielectric comprising a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone, wherein:
the ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5;
a net dopant concentration of a center portion of the body zone is higher than a net dopant concentration of an end portion of the body zone, the center portion located in a center part of the body zone along the vertical direction, the end portion located in an end part of the body zone along the vertical direction and adjoining the source zone; and
a thickness of the gate dielectric part interposed between the gate electrode and the end portion of the body zone along the lateral direction is greater than a thickness of the gate dielectric part interposed between the gate electrode and the center portion of the body zone along the lateral direction.

2. The semiconductor device of claim 1 , wherein the minimum thickness of the gate dielectric part is at most 20 nm and the maximum thickness of the source dielectric part is at least 10 nm.

3. The semiconductor device of claim 1 , wherein the trench dielectric has a bird's beak structure tapering from the source dielectric part to the gate dielectric part.

4. The semiconductor device of claim 1 , wherein the trench dielectric comprises silicon oxide.

5. The semiconductor device of claim 1 , wherein the gate electrode comprises polycrystalline silicon.

6. The semiconductor device of claim 1 , wherein the body zone has an average net dopant concentration of at least 1*10 17 cm −3 .

7. The semiconductor device of claim 1 , wherein the body zone has a net dopant concentration peak profile along the vertical direction, which declines from the peak towards the source zone, which declines from the peak towards the drift zone, and which has a peak net dopant concentration of at least 5*10 17 cm −3 .

8. The semiconductor device of claim 7 , wherein the maximum of the net dopant concentration profile is located in a center part of the body zone along the vertical direction.

9. The semiconductor device of claim 1 , wherein the length of the body zone along the vertical direction is greater than 500 nm.

10. The semiconductor device of claim 1 , wherein the trench gate structure further comprises a field electrode.

11. The semiconductor device of claim 1 , wherein the semiconductor device is an integrated circuit comprising the insulated gate field effect transistor cells and further circuit elements, at least one of the further circuit elements comprising a transistor having a gate dielectric with a thickness varying at most 10% of the minimum thickness of the gate dielectric part.

12. The semiconductor device of claim 1 , further comprising an edge termination electrode adjoining a field dielectric within an edge termination trench.

13. The semiconductor device of claim 1 , wherein the threshold voltage of the at least one of the vertical insulated gate field effect transistor cells is in a range of 1 V to 5 V.

14. A method of manufacturing a semiconductor device comprising a semiconductor body including insulated gate field effect transistor cells, the method comprises forming of at least one of the insulated gate field effect transistor cells by
forming a drift zone of the first conductivity type,
forming a body zone of a second, complementary conductivity type,
forming a source zone of a first conductivity type,
forming a trench gate structure extending into the semiconductor body through the body zone along a vertical direction, and
forming, within the gate trench structure, a trench dielectric and a gate electrode separated from the semiconductor body by the trench dielectric, the trench dielectric comprising a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone, wherein:
the trench dielectric is formed such that the ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5;
a net dopant concentration of a center portion of the body zone is higher than a net dopant concentration of an end portion of the body zone, the center portion located in a center part of the body zone along the vertical direction, the end portion located in an end part of the body zone along the vertical direction and adjoining the source zone; and
a thickness of the gate dielectric part interposed between the gate electrode and the end portion of the body zone along the lateral direction is greater than a thickness of the gate dielectric part interposed between the gate electrode and the center portion of the body zone along the lateral direction.

15. The method of claim 14 , wherein the minimum thickness of the gate dielectric part is at most 20 nm and the maximum thickness of the source dielectric part is at least 10 nm.

16. The method of claim 14 , further comprising performing a wet oxidation process such that the ratio of a maximum thickness of the source dielectric part along the lateral direction and the minimum thickness of the gate dielectric part along the lateral direction becomes at least 1.5.

17. The method of claim 14 , further comprising forming, in addition to the insulated gate field effect transistor cells, further circuit elements, at least one of the circuit elements comprising a transistor having a gate dielectric with a thickness varying at most 10% of the minimum thickness of the gate dielectric part.

18. A method of manufacturing a semiconductor device comprising a semiconductor body, the method comprising
forming a trench within the semiconductor body,
performing a first oxidation process to form an oxide layer lining an inner wall of the trench,
filling the trench with an electrode material, and
performing, after filling the trench, a second oxidation process such that the oxide layer has a bird's beak structure tapering from a trench opening into the trench.

19. The method of claim 18 , wherein the semiconductor body is of silicon.

20. The method of claim 18 , wherein the electrode material is of polycrystalline silicon.

21. The semiconductor device of claim 9 , wherein the length of the source zone along the vertical direction is less than or equal to 200 nm.

Assignees

• Infineon Technologies Ag

Inventors

• Decker Stefan
• Lanzerstorfer Sven
• Meyer Thorsten
• Zink Robert

Classifications

• H01L29/407

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/7811

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/7813 Primary

  Electricity · mapped topic