Transistor with Field Electrodes and Improved Avalanche Breakdown Behavior

Patent metadata

Field	Value
Publication number	US-2016365441-A1
Application number	US-201615182244-A
Country	US
Kind code	A1
Filing date	Jun 14, 2016
Priority date	Jun 15, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

A transistor cell includes, in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second doping type, and a drain region of the first doping type. The body region is arranged between the source and drift regions. The drift region is arranged between the body and drain regions. A gate electrode is adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode is dielectrically insulated from the drift region by a field electrode dielectric. The drift region includes an avalanche region having a higher doping concentration than sections of the drift region adjacent the avalanche region and which is spaced apart from the field electrode dielectric in a direction perpendicular to the current flow direction. The field electrode is arranged in a needle-shaped trench.

First claim

What is claimed is:

1 . A transistor device comprising at least one transistor cell, wherein the at least one transistor cell comprises:
in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second doping type, and a drain region of the first doping type, wherein the body region is arranged between the source region and the drift region, and wherein the drift region is arranged between the body region and the drain region; a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and a field electrode dielectrically insulated from the drift region by a field electrode dielectric, wherein the drift region comprises an avalanche region which has a higher doping concentration than sections of the drift region adjacent the avalanche region and is spaced apart from the field electrode dielectric in a direction perpendicular to a current flow direction of the transistor device, wherein the field electrode is arranged in a needle-shaped trench.

2 . The transistor device of claim 1 , wherein a vertical dimension of the needle-shaped trench is at least 2 times a maximum lateral dimension of the needle-shaped trench.

3 . The transistor device of claim 1 , wherein the field electrode is arranged in a trench having a bottom in a bottom plane of the semiconductor body, and wherein the avalanche region includes at least one section that is closer to the bottom plane than to a surface of the semiconductor body defined by the source region.

4 . The transistor device of claim 3 , wherein each section of the avalanche region is closer to the bottom plane than to the surface of the semiconductor body defined by the source region.

5 . The transistor device of claim 3 , wherein a distance between at least one section of the avalanche region and the bottom plane is less than 30% of a distance between the bottom plane and the surface of the semiconductor body defined by the source region.

6 . The transistor device of claim 3 , wherein a distance between at least one section of the avalanche region and the bottom is less than 50% of a distance between the bottom plane and the gate electrode.

7 . The transistor device of claim 3 , wherein the avalanche region is spaced apart from a pn junction between the body region and the drift region in the current flow direction of the transistor device.

8 . The transistor device of claim 7 , wherein the bottom plane is spaced apart from the pn junction.

9 . The transistor device of claim 1 , wherein a ratio between a maximum doping concentration of the avalanche region and a doping concentration of those sections of the drift region adjacent the avalanche region is between 2 and 10.

10 . The transistor device of claim 8 , wherein a ratio between a maximum doping concentration of the avalanche region and a doping concentration of those sections of the drift region adjacent the avalanche region is between 4 and 7.

11 . The transistor device of claim 1 , wherein the current flow direction of the transistor device is a vertical direction of the semiconductor body.

12 . The transistor device of claim 1 , wherein the gate electrode and the field electrode are arranged in a first trench of the semiconductor body.

13 . The transistor device of claim 12 , further comprising:
a source electrode arranged in a second trench spaced apart from the first trench and electrically connected to the source region and the body region, wherein the avalanche region is arranged below the second trench in the current flow direction of the transistor device.

14 . The transistor device of claim 1 , wherein the field electrode is arranged in a first trench of the semiconductor body and the gate electrode is arranged in a second trench spaced apart from the first trench.

15 . The transistor device of claim 14 , wherein the avalanche region is arranged below the second trench in the current flow direction of the transistor device.

16 . The transistor device of claim 14 , further comprising:
a source electrode arranged in a third trench spaced apart from the first trench and electrically connected to the source region and the body region, wherein the avalanche region is arranged below the third trench in the current flow direction of the transistor device.

17 . The transistor device of claim 1 , wherein the transistor device comprises a plurality of transistor cells.

18 . The transistor device of claim 1 , wherein the gate electrode and the field electrode are dielectrically insulated from one another.

19 . The transistor device of claim 1 , wherein the gate electrode and the field electrode are electrically connected.

20 . A method for forming a transistor device comprising at least one transistor cell, the method comprising:
forming in a semiconductor body in a drift region of a transistor cell an avalanche region, the avalanche region having a higher doping concentration than sections of the drift region adjacent the avalanche region, the avalanche region being spaced apart, in a direction perpendicular to a current flow direction of the transistor device, from a field electrode dielectric dielectrically insulating a field electrode from the drift region and, the avalanche region being spaced apart in the current flow direction of the transistor device from a pn junction between a body region and the drift region, the avalanche region including at least one section that is closer to a bottom plane than to a surface of the semiconductor body; and arranging the field electrode in a trench having a bottom in the bottom plane, wherein forming the avalanche region comprises forming a trench in the semiconductor body, implanting dopant atoms via a bottom of the trench into the drift region, and annealing at least those regions of the drift region into which the dopant atoms have been implanted.

21 . The method of claim 20 , further comprising:
forming a source region adjoining the body region; and forming a source electrode in the trench such that the source electrode is electrically connected to the source region and the body region.

22 . The method of claim 20 , further comprising:
forming a source region adjoining the body region; and forming a gate electrode in the trench such that the gate electrode is dielectrically insulated from the body region.

23 . The method of claim 20 , wherein the trench in which the field electrode is arranged is a needle-shaped trench.

24 . A method for forming a transistor device comprising at least one transistor cell, the method comprising:
forming in a semiconductor body in a drift region of the transistor cell an avalanche region which has a higher doping concentration than sections of the drift region adjacent the avalanche region, wherein forming the avalanche region comprises forming the avalanche region such that the avalanche region is spaced apart, in a direction perpendicular to a current flow direction, from a field electrode dielectric dielectrically insulating a field electrode from the drift region and, in the current flow direction, from a pn junction between a body region and the drift region, and that the avalanche region includes at least one section that is closer to a bottom plane than to a surface of the semiconductor body, wherein the field electrode is arranged in a trench having a bottom in the bottom plane

Assignees

• Infineon Technologies Ag

Inventors

• Siemieniec Ralf
• Zundel Markus
• Bach Karl-Heinz
• Hirler Franz
• Kampen Christian
• Schustereder Werner

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title