Semiconductor interconnect structure with double conductors

Patent metadata

Field	Value
Publication number	US-9837350-B2
Application number	US-201615097033-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Apr 12, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

First claim

What is claimed is:

1. A method for forming a semiconductor interconnect structure comprising:
forming a first conductive layer in a recess of a dielectric layer;
forming a second conductive layer disposed on the first conductive layer; and
forming a wetting layer with a thickness between approximately 5 angstroms and 40 angstroms between the first conductive layer and the dielectric; wherein
the wetting layer comprises cobalt.

2. The method of claim 1 further comprising:
forming a barrier layer disposed on the first conductive layer, wherein the barrier layer serves as a barrier to electromigration between the first conductive layer and the second conductive layer.

3. The method of claim 2 wherein:
the barrier layer is formed from the second conductive layer.

4. The method of claim 2 wherein:
the barrier layer is comprised of tantalum nitride.

5. The method of claim 4 wherein:
the barrier layer is disposed on the first conductive layer via a physical vapor deposition or an atomic layer deposition.

6. The method of claim 2 wherein:
the barrier layer is selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), and cobalt tungsten phosphide (CoWP).

7. The method of claim 1 wherein:
the first conductive layer comprises copper; and
the second conductive layer comprises cobalt.

8. The method of claim 1 wherein:
the first conductive layer is selected from the group consisting of cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), and various alloys thereof; and
the second conductive layer is selected from the group consisting of ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), and various alloys thereof.

9. The method of claim 1 further comprising:
forming a diffusion layer with a thickness between approximately 5 angstroms and 40 angstroms on the dielectric; wherein
the first conductive layer is formed on the diffusion layer.

10. The method of claim 9 wherein:
the diffusion layer is selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), pyroxmangite (MnSiO 3 ), and tantalum manganese oxide (TaMnO).

11. The method of claim 1 further comprising:
performing a chemical-mechanical planarization process before forming the second conductive layer on the first conductive layer.

12. The method of claim 11 wherein:
the chemical-mechanical planarization process is configured to overpolish to form a recess.

13. The method of claim 1 further comprising:
performing a chemical-mechanical planarization process after forming the second conductive layer on the first conductive layer.

Assignees

• IBM

Inventors

• Briggs Benjamin D
• Nogami Takeshi
• Patlolla Raghuveer R

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title