Iterative simulation with DFT and non-DFT

Patent metadata

Field	Value
Publication number	US-9836563-B2
Application number	US-201414498492-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 26, 2013
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.

First claim

The invention claimed is:

1. An EDA tool comprising:
a data processor;
storage configured to provide computer program instructions to the processor, including:
a controller module causing a plurality of simulation modules to perform an EDA simulation at a plurality of different simulation scales, the plurality of simulation modules including:
a first set of one or more ab initio simulation modules; and
a second set of one of more simulation modules at a second simulation scale larger than the first simulation scale of the first set of one or more simulation modules,
wherein the controller module causes the plurality of simulation modules to iterate between the first set of one or more ab initio simulation modules and the second set of one of more simulation modules including any of drift-diffusion simulation modules, wave function formalism quantum transport simulation modules, Wigner function quantum transport simulation modules, Boltzmann transport simulation modules.

2. The EDA tool of claim 1 , wherein the plurality of simulation modules automatically simulate a previously unmanufactured set of materials comprising at least one transistor in the EDA simulation to satisfy a target performance specification.

3. The EDA tool of claim 1 , wherein the plurality of simulation modules automatically simulate a previously unmanufactured ratio of a set of materials comprising at least one transistor in the EDA simulation to satisfy a target performance specification.

4. The EDA tool of claim 1 , wherein the second set of one of more Boltzmann transport simulation modules includes one or more Monte Carlo Boltzmann transport simulation modules.

5. The EDA tool of claim 1 , wherein the second set of one of more Boltzmann transport simulation modules includes one or more deterministic Boltzmann transport simulation modules.

6. A computer-implemented method comprising:
causing a plurality of simulation modules to perform an EDA simulation at a plurality of different simulation scales, the plurality of simulation modules including:
a first set of one or more ab initio simulation modules; and
a second set of one of more simulation modules at a second simulation scale larger than the first simulation scale of the first set of one or more simulation modules; and

causing the plurality of simulation modules to iterate between the first set of one or more ab initio simulation modules and the second set of one of more simulation modules including any of drift-diffusion simulation modules, wave function formalism quantum transport simulation modules, Wigner function quantum transport simulation modules, Boltzmann transport simulation modules.

7. The computer-implemented method of claim 6 , wherein the plurality of simulation modules automatically simulate a previously unmanufactured set of materials comprising at least one transistor in the EDA simulation to satisfy a target performance specification.

8. The computer-implemented method of claim 6 , wherein the plurality of simulation modules automatically simulate a previously unmanufactured ratio of a set of materials comprising at least one transistor in the EDA simulation to satisfy a target performance specification.

9. The computer-implemented method of claim 6 , wherein the second set of one of more Boltzmann transport simulation modules includes one or more Monte Carlo Boltzmann transport simulation modules.

10. The computer-implemented method of claim 6 , wherein the second set of one of more Boltzmann transport simulation modules includes one or more deterministic Boltzmann transport simulation modules.

Assignees

• Synopsys Inc

Inventors

• Liu Jie
• Moroz Victor
• Shaughnessy-Culver Michael C
• Smith Stephen Lee
• Oh Yong-Seog
• Balasingam Pratheep
• Ma Terry Sylvan Kam-Chiu

Classifications

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/3312

  Timing analysis · CPC title