Panel level fabrication of package substrates with integrated stiffeners

Patent metadata

Field	Value
Publication number	US-9832860-B2
Application number	US-201414498958-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

First claim

What is claimed is:

1. A package substrate, comprising:
a substrate having a first plurality of pads on a first surface and a second plurality of pads on a second surface opposite of the first surface;
an adhesion layer disposed on the first surface and around the first plurality of pads; and
a stiffener disposed on top of the adhesion layer and around the first plurality of pads, the stiffener having a tab comprising a first portion of an outer edge of the stiffener that extends to an edge of the substrate, the tab having a length extending along a portion of the edge of the substrate, wherein a second portion of the outer edge of the stiffener does not extend to the edge of the substrate.

2. The package substrate of claim 1 , wherein the first portion of the outer edge of the stiffener is located on a side of the stiffener.

3. The package substrate of claim 1 , wherein the first portion of the outer edge of the stiffener is located at a corner of the stiffener.

4. The package substrate of claim 1 , wherein the stiffener is formed of a metal.

5. A device package, comprising:
a substrate having a first plurality of pads on a first surface and a second plurality of pads on a second surface opposite of the first surface;
a semiconductor die coupled to the first plurality of pads;
a second level interconnect (SLI) structure coupled to the second plurality of pads;
an adhesion layer disposed on the first surface and around the first plurality of pads and the semiconductor die; and
a stiffener disposed on top of the adhesion layer and around the first plurality of pads and the semiconductor die, the stiffener having a tab comprising a first portion of an outer edge of the stiffener that extends to an edge of the substrate, the tab having a length extending along a portion of the edge of the substrate, wherein a second portion of the outer edge of the stiffener does not extend to the edge of the substrate.

6. The device package of claim 5 , further comprising an underfill material disposed between the die and the first surface of the substrate.

7. The device package of claim 6 , wherein the underfill material contacts an inner edge of the stiffener.

8. The device package of claim 7 , further comprising an underfill keep out zone that is a region of the first surface disposed between the inner edge of the stiffener and the first plurality of pads.

9. The device package of claim 8 , wherein the distance between the inner edge of the stiffener and the first plurality of pads is less than 2 mm.

10. The device package of claim 7 , wherein the underfill material has a planar top surface.

11. The device package of claim 10 , wherein the planar top surface of the underfill material is below the top surface of the stiffener.

12. The device package of claim 10 , wherein the planar top surface is substantially horizontal.

13. The device package of claim 5 , wherein the die extends above the stiffener.

14. The device package of claim 5 , wherein the first portion of the outer edge of the stiffener is located on a side of the stiffener.

15. The device package of claim 5 , wherein the first portion of the outer edge of the stiffener is located at a corner of the stiffener.

Assignees

• Intel Corp

Inventors

• Starkston Robert
• Guzek John
• Nardi Patrick
• Jones Keith
• Soto Gonzalez Javier

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W76/40

  Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title