Semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9831260-B2
Application number	US-201715403829-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Mar 2, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a peripheral circuit gate pattern on a first substrate;
an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern;
a cell array structure on the peripheral circuit gate pattern;
a second substrate between the peripheral circuit gate pattern and the cell array structure; and
a via that is in contact with the impurity region and disposed between the first substrate and the second substrate,
wherein the via electrically connects the first and second substrates to each other.

2. The semiconductor memory device of claim 1 , wherein the impurity region has a conductivity different from that of the first substrate.

3. The semiconductor memory device of claim 1 , further comprising:
a source/drain region on a side of the peripheral circuit gate pattern in the first substrate; and
a contact plug that is in contact with the source/drain region and disposed between the first substrate and the second substrate,
wherein the via includes a top surface coplanar with a bottom surface of the second substrate, and
wherein the contact plug includes a top surface lower than the bottom surface of the second substrate relative to the first substrate.

4. The semiconductor memory device of claim 1 , wherein the impurity region comprises a first impurity region and a second impurity region enveloping the first impurity region,
wherein the first impurity region has an impurity concentration greater than that of the second impurity region.

5. The semiconductor memory device of claim 1 , wherein
the first substrate comprises a peripheral circuit region and a ground region in the peripheral circuit region,
the second substrate comprises a cell array region vertically overlapping the peripheral circuit region, and
the via is disposed between the cell array region and the ground region.

6. The semiconductor memory device of claim 1 , wherein
the first substrate comprises a peripheral circuit region disposed on a portion of a central part of the first substrate and a ground region disposed on a portion of a circumferential part of the first substrate,
the second substrate comprises a cell array region vertically overlapping the peripheral circuit region and a contact region vertically overlapping the ground region, and
the via is disposed between the contact region and the ground region.

7. The semiconductor memory device of claim 6 , wherein
the via comprises a first sidewall and a second sidewall facing each other,
the second substrate comprises a first side surface and a second side surface facing each other,
wherein the second sidewall of the via is coplanar with the second side surface of the second substrate, and the first sidewall of the via is disposed between the first and second side surfaces of the second substrate.

8. The semiconductor memory device of claim 7 , further comprising an isolation pattern that is in contact with the second sidewall of the via and wraps the second side surface of the second substrate,
wherein the isolation pattern has a thickness substantially equal to a sum of a thickness of the via and a thickness of the second substrate.

9. The semiconductor memory device of claim 1 , further comprising an isolation pattern wrapping a side surface of the second substrate.

10. The semiconductor memory device of claim 9 , wherein the first substrate has a planar area substantially equal to a sum of a planar area of the second substrate and a planar area of the isolation pattern.

11. The semiconductor memory device of claim 9 , wherein the isolation pattern has a thickness greater than that of the second substrate.

12. The semiconductor memory device of claim 1 , wherein the cell array structure comprises:
a stack structure including gate patterns that are stacked on the second substrate;
a vertical channel region penetrating the stack structure; and
a charge storage structure between the vertical channel region and each of the gate patterns.

13. A semiconductor memory device, comprising:
a substrate including a peripheral circuit region and a ground region spaced apart from the peripheral circuit region, the ground region corresponding to a portion of an edge of the substrate;
an impurity region in the ground region of the substrate;
an interlayer dielectric layer on the substrate and exposing the impurity region;
a silicon structure including a first portion in the interlayer dielectric layer and in contact with the impurity region and a second portion extending from the first portion onto a top surface of the interlayer dielectric layer, the silicon structure being electrically connected to the substrate; and
a cell array structure on the second portion of the silicon structure.

14. The semiconductor memory device of claim 13 , wherein the impurity region has conductivity different from that of the substrate.

15. The semiconductor memory device of claim 13 , wherein the second portion of the silicon structure comprises a cell array region and a contact region around the cell array region,
wherein the first portion of the silicon structure is disposed between the contact region of the second portion and the ground region of the substrate.

16. A semiconductor memory device, comprising:
a first substrate;
an impurity region in the first substrate;
an interlayer dielectric layer on the first substrate;
a second substrate on the interlayer dielectric layer;
a cell array region on the second substrate that overlaps the impurity region; and
a via that penetrates the interlayer dielectric layer so as to electrically connect the second substrate to the first substrate.

17. The semiconductor memory device of claim 16 , further comprising:
a gate pattern on the first substrate;
source and drain regions in the first substrate on opposing sides of the gate pattern; and
a contact plug on one of the source and drain regions.

18. The semiconductor memory device of claim 17 , wherein a top surface of the via is higher than a top surface of the contact plug relative to the first substrate.

19. The semiconductor device of claim 16 , wherein a conductivity of the impurity region is different than a conductivity of the first substrate;
wherein the impurity region comprises a first impurity region and a second impurity region, the second impurity region enveloping the first impurity region; and
wherein an impurity concentration of the first impurity region is greater than an impurity concentration of the second impurity region.

20. The semiconductor memory device of claim 16 , further comprising:
an isolation pattern on a side surface of the second substrate and that partially penetrates the interlayer dielectric layer without extending through the interlayer dielectric layer.

Assignees

• Zhang Gang
• Kim Hyuk
• Kwon Yong-Hyun
• Park Sangwuk
• Samsung Electronics Co Ltd

Inventors

• Zhang Gang
• Kim Hyuk
• Kwon Yong-Hyun
• Park Sangwuk

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L2924/1438

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L2027/11861

  Electricity · mapped topic