JFET device structures and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9831246-B2
Application number	US-201313925471-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	Dec 11, 2008
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

First claim

What is claimed is:

1. A transistor comprising:
a substrate comprising a source and a drain, wherein the substrate comprises a semiconductor directly on top of an insulator forming an interface, and wherein the insulator is doped;
a doped channel formed in the semiconductor between the source and the drain, the channel configured to pass current between the source and the drain, wherein the semiconductor is doped by out diffusion from the insulator such that an ion concentration in the semiconductor is highest at the interface with the insulator, and a highest ion concentration in the insulator is no higher than the ion concentration in the semiconductor at the interface with the insulator;
a gate formed directly on the channel; and
dielectric spacers located on each side of the gate, wherein the source and the drain are spatially separated from the gate so that the gate is not located over the source and drain.

2. The transistor of claim 1 , wherein the source and drain are separated from the gate a distance approximately equal to the width of the dielectric spacer.

3. The transistor of claim 1 , wherein the width of the dielectric spacer is approximately ⅓ the length of the gate.

4. The transistor of claim 1 , wherein the width of the dielectric spacer is less than ⅓ the length of the gate.

5. The transistor of claim 1 , wherein the substrate is silicon-on-insulator.

6. The transistor of claim 1 , wherein the substrate is silicon-on-sapphire.

7. The transistor of claim 1 , wherein the insulator is doped with boron to create a boron-rich oxide under the channel region.

8. A transistor comprising:
a substrate, wherein the substrate is doped to form a p-type insulator;
silicon formed over the substrate;
a channel formed in the silicon, wherein the channel comprises a first p-type region, a second p-type region, and an n-type region, the first p-type region formed over the n-type region, and the n-type region formed over the second p-type region, wherein the second p-type region is formed directly on the p-type insulator at an interface by out diffusion of doped ions from the p-type insulator such that an ion concentration in the second p-type region is highest at the interface with the p-type insulator, and a highest ion concentration in the p-type insulator is no higher than the ion concentration in the second p-type region at the interface with the p-type insulator;
a gate formed over the channel; and
a source and drain formed in the silicon on opposing sides of the channel, wherein the source and drain do not extend under the gate.

9. The transistor of claim 8 , comprising insulative spacers located on each side of the gate.

10. The transistor of claim 9 , wherein the drain and source are spatially separated from the gate a distance approximately equal to the width of the spacers.

11. The transistor of claim 10 , wherein the width of each spacer is approximately ⅓ the length of the gate.

12. The transistor of claim 8 , wherein the gate is doped p-type to form an n-JFET enhancement mode device.

13. The transistor of claim 8 , wherein the n-type region doping level is approximately less than 1e16/cm3.

14. A transistor comprising:
a substrate, wherein the substrate is doped to form an n-type insulator;
silicon formed over the substrate;
a channel formed in the silicon, wherein the channel comprises a first n-type region, a second n-type region, and a p-type region, the first n-type region formed over the p-type region, and the p-type region formed over the second n-type region, wherein the second n-type region is formed directly on the n-type insulator at an interface by out diffusion of doped ions from the n-type insulator such that an ion concentration in the second n-type region is highest at the interface with the n-type insulator, and a highest ion concentration in the n-type insulator is no higher than the ion concentration in the second n-type region at the interface with the n-type insulator;
a gate formed over the channel; and
a source and drain formed in the silicon on opposing sides of the channel, wherein the source and drain do not extend under the gate.

15. The transistor of claim 14 , comprising insulative spacers located on each side of the gate.

16. The transistor of claim 15 , wherein the drain and source are spatially separated from the gate a distance approximately equal to the width of the spacers.

17. The transistor of claim 16 , wherein the width of each spacer is approximately ⅓ the length of the gate.

18. The transistor of claim 14 , wherein the gate is doped n-type to form a p-JFET enhancement mode device.

19. The transistor of claim 14 , wherein the p-type region doping level is approximately less than 1e16/cm3.

20. The transistor of claim 14 , wherein the second n-type region forms the interface of the silicon and the substrate material.

21. A semiconductor device comprising:
a first level of one or more transistors, the first level comprising:
a first insulative substrate;
a first semiconductor formed over the substrate;
a first gate formed directly on the first semiconductor, wherein the first gate and the first semiconductor form a p-n junction; and
first insulative spacers formed on each side of the gate; and

a second level comprising one or more transistors, the second level comprising:
a second insulative substrate formed over the first level;
a second semiconductor formed over the second substrate;
a second gate formed directly on the second semiconductor, wherein the second gate and the second semiconductor form a p-n junction; and
second insulative spacers formed on each side of the second gate,
wherein each of the first and second semiconductors comprise a respective source, a drain, and a channel,
wherein the source and drain of the first and second semiconductors are separated from their corresponding gates a distance approximately ⅓ the length of the corresponding gates, and
wherein the second gates of p-type and n-type transistors of the second level are shorter than the first gates of the transistors of the first level.

22. The semiconductor device of claim 21 , wherein the source and drain of the first and second semiconductors do not extend under the first and second gates, respectively.

23. The semiconductor device of claim 21 , wherein the first level of transistors comprises p-type transistors and the second level of transistors comprises n-type transistors.

24. The semiconductor device of claim 21 , wherein the first level of transistors comprises n-type transistors and the second level of transistors comprises p-type transistors.

25. The semiconductor device of claim 23 , wherein transistors of the first level of transistors and transistors of the second level of transistors are coupled together to form a logic device.

26. The semiconductor device of claim 24 , wherein transistors of the first level of transistors and transistors of the second level of transistors are coupled together to form a logic device.

27. A semiconductor device comprising:
a first level comprising a first plurality of transistors; and
a second level formed over the first level, the second level comprising a second plurality of transistors, wherein each of the first and second plurality of transistors comprises:
a doped insulative material, wherein the doped insulative material of the first level has a higher concentrat

Assignees

• Micron Technology Inc

Inventors

• Mouli Chandra

Classifications

• H10P36/07

  of silicon-on-insulator structures · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/17

  characterised by the semiconductor material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title