Normally off power electronic component

Patent metadata

Field	Value
Publication number	US-9418984-B2
Application number	US-201314104317-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Dec 14, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.

First claim

The invention claimed is:

1. A power electronic component, comprising:
a conductive plate;
a first semiconductor chip having first and second faces opposite to each other, the second face being arranged on and supported by the conductive plate;
a second semiconductor chip supported by the conductive plate;
a high-voltage normally on transistor formed in the second semiconductor chip; and
a low-voltage normally off transistor formed in the first semiconductor chip and coupled in cascode configuration with the normally on transistor, the normally off transistor being a bottom source transistor having a drain terminal and a gate terminal on the first face of the first semiconductor chip and a source terminal on the second face of the first semiconductor chip, the source terminal being conductively connected to the conductive plate.

2. A component according to claim 1 , wherein the normally off transistor is an LDMOS transistor.

3. A component according to claim 1 , comprising a control circuit integrated in the first semiconductor chip.

4. A component according to claim 3 , wherein the control circuit is coupled to the normally on transistor and to the normally off transistor and is configured to slow down a charge transfer toward a gate-source capacitance of the normally off transistor during a turn-on stage and to slow down a charge removal from a gate-source capacitance of the normally on transistor during a turn-off stage.

5. A component according to claim 4 , having a first connection terminal and a second connection terminal; wherein:
the control circuit includes a first resistor, a capacitor and a second resistor;
the first resistor is electrically coupled between the gate terminal of the normally off transistor and the first connection terminal;
the capacitor is electrically coupled between the gate terminal of the normally off transistor and a drain terminal of the normally on transistor; and
the second resistor is electrically coupled between a control terminal of the normally on transistor and the source terminal of the normally off transistor.

6. A component according to claim 1 , wherein the normally on transistor is a GaN HEMT transistor.

7. A component according to claim 1 , wherein the normally on transistor is a horizontal bottom gate JFET transistor.

8. A component according to claim 1 , wherein the normally on transistor is a lateral JFET transistor.

9. A component according to claim 8 , further comprising a Schottky diode integrated in the second semiconductor chip.

10. A component according to claim 9 , wherein:
the second semiconductor chip includes a drift layer;
the normally on transistor includes a source region, a drain region, a gate region and a channel region, accommodated in the drift layer and flush with a surface of the drift layer;
an anode terminal of the Schottky diode is arranged on the drift layer at a distance from the normally on transistor; and
a cathode terminal of the Schottky diode is defined by the drain terminal of the normally on transistor.

11. A component according to claim 10 , wherein the anode terminal of the Schottky diode is connected to the source terminal of the normally on transistor.

12. A packaged power electronic component, comprising:
a conductive plate;
a first semiconductor chip having first and second faces opposite to each other, the second face being arranged on the conductive plate;
a second semiconductor chip arranged on the conductive plate;
a high-voltage normally on transistor formed in the second semiconductor chip;
a low-voltage normally off transistor formed in the first semiconductor chip and coupled in cascode configuration with the normally on transistor, the normally off transistor being a bottom source transistor having a drain terminal and a gate terminal on the first face of the first semiconductor chip and a source terminal on the second face of the first semiconductor chip, the source terminal being conductively connected to the conductive plate;
a plastic casing that houses the conductive plate, first semiconductor chip, normally on transistor, and normal off transistor; and
first and second leads electrically coupled to the normal on and normally off transistors, respectively, and extending outwardly from the plastic casing.

13. The packaged power electronic component of claim 12 , comprising a control circuit integrated in the first semiconductor chip, coupled to the normally on transistor and to the normally off transistor, and configured to slow down a charge transfer toward a gate-source capacitance of the normally off transistor during a turn-on stage and to slow down a charge removal from a gate-source capacitance of the normally on transistor during a turn-off stage.

14. The packaged power electronic component of claim 13 , wherein the control circuit includes:
a first resistor electrically coupled between the gate terminal of the normally off transistor and the first lead;
a capacitor electrically coupled between the gate terminal of the normally off transistor and a drain terminal of the normally on transistor; and
a second resistor electrically coupled between a control terminal of the normally on transistor and the source terminal of the normally off transistor.

15. The packaged power electronic component of claim 12 , wherein the component further includes a Schottky diode integrated in the second semiconductor chip.

16. The packaged power electronic component of claim 15 , wherein:
the second semiconductor chip includes a drift layer;
the normally on transistor includes a source region, a drain region, a gate region and a channel region, accommodated in the drift layer and flush with a surface of the drift layer;
an anode terminal of the Schottky diode is arranged on the drift layer at a distance from the normally on transistor; and
a cathode terminal of the Schottky diode is defined by the drain terminal of the normally on transistor.

17. The packaged power electronic component of claim 16 , wherein the anode terminal of the Schottky diode is connected to the source terminal of the normally on transistor.

18. A power electronic component, comprising:
a conductive plate;
a first semiconductor chip having first and second faces opposite to each other, the second face being arranged on the conductive plate;
a second semiconductor chip arranged on the conductive plate;
a high-voltage normally on transistor formed in the second semiconductor chip; and
a low-voltage normally off transistor formed in the first semiconductor chip and coupled in cascade configuration with the normally on transistor, the normally off transistor being a bottom source transistor having a drain terminal and a gate terminal on the first face of the first semiconductor chip and a source terminal on the second face of the first semiconductor chip, the source terminal being conductively connected to the conductive plate, wherein the normally on transistor is formed in a second semiconductor chip arranged on the conductive plate and the normally on transistor is a GaN HEMT transistor.

19. A component according to claim 18 , wherein the normally off transistor is an LDMOS transistor.

20. A component according to claim 18 , comprising a control circuit integrated in the first semiconductor chip, wherein the control circuit is coupled to the normally on transistor and to the normally off transitory and is configured to slow down a charge transfer toward a gate-source capacitance of the normally off transistor during a t

Assignees

• St Microelectronics Srl

Inventors

• Santangelo Antonello
• Giuffrida Marcello Francesco Salvatore

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title