Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9830990-B2
Application number	US-201715615998-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Oct 17, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of memory cells;
a plurality of plate lines respectively connected to the plurality of memory cells;
a plate line driver operable to drive the plurality of plate lines individually; and
a memory controller operable to control access to the plurality of memory cells,
wherein the plurality of memory cells each include:
an inverter loop connected between a first node and a second node;
a first access transistor connected between the first node and a bit line;
a second access transistor connected between the second node and an inverted bit line;
a first ferroelectric capacitor connected between the first node and a plate line; and
a second ferroelectric capacitor connected between the second node and the plate line,

wherein, when restoring/recalling data in the memory cells, the memory controller pulse-drives the plurality of plate lines sequentially by use of the plate line driver and meanwhile, before pulse-driving an uncharged plate line by use of the plate line driver, the memory controller performs charge sharing between a charged plate line and the uncharged plate line.

2. The semiconductor memory device according to claim 1 , further comprising:
a plurality of transmission gates each connected between adjacent plate lines,
wherein, before pulse-driving the uncharged plate line by use of the plate line driver, the memory controller turns on a transmission gate between the charged plate line and the uncharged plate line.

3. The semiconductor memory device according to claim 1 , wherein
when an output enable signal from the plate line driver turns to a first logic level, one of adjacent plate lines is charged up to a first voltage,
when the output enable signal turns to a second logic level, the one of the adjacent plate lines is brought into a floating state,
when the transmission gate is turned on, a path between the adjacent plate lines conducts, and charge sharing is performed until voltages on the adjacent plate lines are equal,
when the transmission gate is turned off, the path between the adjacent plate lines is cut off, and
when the output enable signal turns to the first logic level again, another of the adjacent plate lines is charged up to a first voltage, and the one of the adjacent plate lines is discharged down to a second voltage.

4. The semiconductor memory device according to claim 1 , wherein
the plate line driver drives the plurality of plate lines sequentially, one at a time.

5. The semiconductor memory device according to claim 1 , wherein
the plate line driver drives the plurality of plate lines a plurality of them at a time, in a plurality of steps.

6. The semiconductor memory device according to claim 1 , further comprising:
a plurality of second plate lines respectively connected to the plurality of memory cells, wherein
the plurality of memory cells each further include:
a third ferroelectric capacitor connected between the first node and a second plate line; and
a fourth ferroelectric capacitor connected between the second node and the second plate line, and

when restoring/recalling data in the memory cells, the memory controller performs, by using the plate line driver, both charge sharing among the plurality of plate lines and charge sharing among the plurality of second plate lines.

7. The semiconductor memory device according to claim 1 , wherein
the inverter loop includes:
a first load transistor of which a source is connected to a first potential terminal, a drain is connected to the first node, and a gate is connected to the second node;
a second load transistor of which a source is connected to the first potential terminal, a drain is connected to the second node, and a gate is connected to the first node;
a first drive transistor of which a source is connected to a second potential terminal, a drain is connected to the first node, and a gate is connected to the second node; and
a second drive transistor of which a source is connected to the second potential terminal, a drain is connected to the second node, and a gate is connected to the first node.

8. The semiconductor memory device according to claim 1 , wherein
the first and second access transistors are each turned on and off according to a voltage applied to a word line connected to a gate thereof.

9. The semiconductor memory device according to claim 1 , wherein
in a write operation in the memory cells, first the first and second access transistors are turned on, and then the bit line and the inverted bit line are held at logic levels corresponding to written data.

10. The semiconductor memory device according to claim 1 , wherein
in a read operation in the memory cells, first the bit line and the inverted bit line are brought into a floating state, and then the first and second access transistors are turned on.

11. The semiconductor memory device according to claim 1 , wherein
in a store operation in the memory cells, the plate lines are pulse-driven so as to determine residual polarization states of the first and second ferroelectric capacitors.

12. The semiconductor memory device according to claim 1 , wherein
in a recall operation in the memory cells, the plate lines are pulse-driven so that voltages that reflect residual polarization states of the first and second ferroelectric capacitors are induced at the first and second nodes.

Assignees

• Rohm Co Ltd

Inventors

• Izumi Shintaro
• Nakagawa Tomoki
• Kawaguchi Hiroshi
• Yoshimoto Masahiko

Classifications

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2259 Primary

  Cell access · CPC title

• G11C29/08

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C14/0072 Primary

  and the nonvolatile element is a ferroelectric element · CPC title