Apparatus and method for controlling execution of processes in a parallel computing system

Patent metadata

Field	Value
Publication number	US-9830195-B2
Application number	US-201414475961-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	Sep 30, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the access requests, based on a result of comparing the progress levels measured by the measuring circuits of the first arithmetic processors.

First claim

What is claimed is:

1. A method for controlling an information processing device including an arbiter and a plurality of arithmetic processors, each arithmetic processor including an arithmetic circuit and a measuring circuit, the measuring circuit including a multiplexer circuit a counter circuit, and an incrementer circuit, the method comprising:
measuring, by the measuring circuit, for each of the plurality of arithmetic processors, a progress level indicating progress of arithmetic processing executed by each arithmetic processor by performing a process including:
causing the counter circuit to hold a first value and output the first value held therein,
causing the incrementer circuit to output a second value obtained by incrementing the first value output by the counter circuit,
causing the multiplexer circuit to select one of the first value and the second value output by the counter circuit and the incrementer circuit, respectively, and to output to the counter circuit the one of the first value and the second value selected by the multiplexer circuit,
causing the multiplexer circuit to, upon receiving from the arithmetic circuit a selection signal indicating that a unit process is completed, select the second value output by the incrementer circuit and output to the counter circuit the second value selected by the multiplexer circuit to increment the first value stored in the counter circuit, and
measuring the first value as the progress level; and

upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, arbitrating, by the arbiter, the access requests based on progress levels measured for the first arithmetic processors that are transmission sources of the access requests.

2. The method of claim 1 , further comprising:
causing the arithmetic circuit to
separate the arithmetic process into a plurality of unit processes, each unit process executed in a unit time by the arithmetic processor,
execute the unit processes, and
output to the multiplexer circuit of the measuring circuit, upon completion of execution of each unit process, a third signal indicating the unit process is finished; and

causing the multiplexer circuit of the measuring circuit to select the second value output by the incrementer circuit and to output to the counter circuit the second value selected by the multiplexer circuit to increment the first value stored in the counter circuit, each time the multiplexer circuit of the measuring circuit receives the selection signal from the arithmetic circuit.

3. The method of claim 1 , further comprising causing the measuring circuit to:
start counting a local time, based on a clock operated by the arithmetic processor, at a first time when the arithmetic processor starts execution of the arithmetic process,
output a value of counted time obtained by the counting, as the progress level for the arithmetic process, to the arbiter at a second time when an access request to the external device is issued by the arithmetic processor, and
interrupt the counting of the local time from the second time to a third time when a reply to the access request is received by the arithmetic processor.

4. An apparatus comprising:
an information processing device, including
an arbiter; and
a plurality of arithmetic processors, each including:
an arithmetic circuit configured to execute an arithmetic process, and
a measuring circuit configured to measure a progress level indicating progress of the arithmetic process executed by the arithmetic circuit, the measuring circuit including a multiplexer circuit, a counter circuit that holds a first value output by the multiplexer circuit and outputs the first value held therein, and an incrementer circuit that outputs a second value obtained by incrementing the first value output by the counter circuit,

wherein
the multiplexer circuit of the measuring circuit is configured to select one of the first value and the second value output by the counter circuit and the incrementer circuit, respectively, and to output to the counter circuit the one of the first value and the second value selected by the multiplexer circuit;
upon receiving from the arithmetic circuit a selection signal indicating that a unit process is completed, the multiplexer circuit selects the second value output by the incrementer circuit and outputs to the counter circuit the second value selected by the multiplexer circuit to increment the first value stored in the counter circuit;
the measuring circuit measures the first value as the progress level; and
the arbiter is configured to, upon receiving first access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, arbitrate the first access requests, based on a comparison result of comparing first progress levels measured by the measuring circuits of the first arithmetic processors that are transmission sources of the first access requests.

5. The apparatus of claim 1 , wherein
the arithmetic circuit outputs as the selection signal a pulse signal, having a high electric potential, to the multiplexer circuit of the measuring circuit.

6. The apparatus of claim 1 , wherein, when a plurality of external devices to which access requests are to be issued are present, upon receiving second access requests to each of the plurality of external devices from second arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the second access requests, based on progress levels measured by the measuring circuits of the second arithmetic processors that are transmission sources of the second access requests to the plurality of external devices.

7. The apparatus of claim 1 ,
further comprising another information processing device, and
wherein the information processing device further includes a transmitter configured to, upon receiving a third access request to an external device controlled by the other information processing device, transmit the progress level measured by the measuring circuit of the arithmetic processor that is a transmission source of the third access request, and an execution request for requesting the external device to execute processing, to the other information processing device.

8. The apparatus of claim 1 ,
wherein the arithmetic circuit is configured to
separate the arithmetic process into a plurality of unit processes, each unit process executed in a unit time by the arithmetic processor,
execute the unit processes, and
output to the multiplexer circuit of the measuring circuit, upon completion of execution of each unit process, a selection signal indicating the unit process is finished; and

wherein the multiplexer circuit selects the second value output by the incrementer circuit and outputs to the counter circuit the second value selected by the multiplexer circuit to increment the first value stored in the counter circuit, each time the multiplexer circuit receives the selection signal from the arithmetic circuit.

9. The apparatus of claim 1 , wherein the measuring circuit is configured to
start counting a local time, based on a clock operated by the arithmetic processor, at a first time when the arithmetic processor starts execution of the arithmetic process,
output a value representing counted time obtained by the counting, as the progress level for the arithmetic process, to the arbiter at a second time when an access request to the external device is issued by the arithmetic processor, and
interrupt the counting of the local time from the second time to a third time when a reply to the access request is received by the arithmetic process

Assignees

• Fujitsu Ltd

Inventors

• Yoshida Yuki
• Kase Masaru
• Shimizu Toshiyuki

Classifications

• G06F13/3625

  using a time dependent access · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F13/374

  using a self-select method with individual priority code comparator · CPC title

• G06F13/372

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title