On-chip traffic prioritization in memory

Patent metadata

Field	Value
Publication number	US-9405711-B2
Application number	US-201313737339-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 9, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

First claim

What is claimed is:

1. A method for traffic prioritization in a memory device, the method comprising:
setting a first memory request priority register in a first processing element of a plurality of processing elements in the memory device to a first priority value based at least in part on a first load-to-use distance hint from a compiler and a first instruction execution rate associated with the first processing element;
setting a second memory request priority register in a second processing element of the plurality of processing elements to a second priority value based at least in part on a second load-to-use distance hint from the compiler and a second instruction execution rate associated with the second processing element;
sending a first memory access request comprising the first priority value from the first processing element to a crossbar interconnect in the memory device, the memory device further comprising: a plurality of memory controllers, each of the plurality of processing elements and each of the plurality of memory controllers being coupled to the crossbar interconnect, the plurality of memory controllers comprising a memory controller that comprises a queue that buffers a plurality of memory access requests to a memory stack comprising a plurality of memory dies stacked together, the plurality of memory access requests buffered in the queue comprising a second memory access request comprising the second priority value;
routing the first memory access request through the crossbar interconnect to the memory controller;
receiving the first memory access request at the memory controller;
determining that the first priority value is greater than the second priority value, wherein the first priority value being greater than the second priority value indicates at least in part that the first instruction execution rate is less than the second instruction execution rate or that the second load-to-use distance hint is greater than the first load-to-use distance hint; and
accessing, by the memory controller, the memory stack based on the first memory access request prior to accessing the memory stack based on the second memory access request.

2. The method of claim 1 , further comprising:
setting the first memory request priority register to the first priority value further based at least in part on an application code hint indicating criticality of a code section.

3. The method of claim 1 , further comprising:
setting the first memory request priority register to the first priority value further based at least in part on a load-store queue depth relative to a load-store queue capacity of a load-store queue in the first processing element.

4. The method of claim 3 , further comprising:
receiving at the memory controller an indication that the load-store queue has reached a threshold level of the load-store queue depth relative to the load-store queue capacity; and
increasing a third priority value of a third memory access request in the queue of the memory controller, wherein the third memory access request is received from the first processing element.

5. The method of claim 1 , further comprising:
setting a progress counter value of a progress counter in the first processing element based at least in part on a number of instructions executed in the first processing element relative to a number of instructions executed in one or more other processing elements of the plurality of processing elements; and
setting the first memory request priority register to the first priority value further based at least in part on the progress counter value.

6. The method of claim 5 , wherein the progress counter is a first progress counter and the progress counter value is a first progress counter value, the method further comprising:
receiving the first progress counter value of the first progress counter at a progress monitor;
determining that the first progress counter value is greater than a second progress counter value of a second progress counter in the second processing element, wherein the first progress counter value being greater than the second progress counter value indicates that a first number of instructions executed in the first processing element is greater than a second number of instructions executed in the second processing element;
decreasing the first priority value of the first memory request priority register; and
increasing the second priority value of the second memory request priority register in the second processing element.

7. The method of claim 1 , further comprising:
receiving a third memory access request at the crossbar interconnect; and
arbitrating between the first memory access request and the third memory access request based at least in part on comparing the first priority value to a third priority value in the third memory access request,
wherein arbitrating comprises:
determining that the first priority value is greater than the third priority value; and
performing one of:
assigning, in accordance with a request-grant protocol, a first scheduling slot to the first memory access request and a second scheduling slot to the third memory access request, the first scheduling slot indicating that the first memory access request will be permitted to pass through the crossbar interconnect prior to the third memory access request, or
permitting the first memory access request to pass through the crossbar interconnect and denying the third memory access request in accordance with a speculative request protocol.

8. The method of claim 1 , further comprising:
adjusting the first priority value based on one or more of:
a number of the plurality of memory access requests in the queue received from the first processing element;
a corresponding priority value of a particular memory access request added most recently to the queue among one or more memory access requests received from the first processing element; or
an age of at least one memory access request in the queue.

9. A method for traffic prioritization in a memory system, the method comprising:
setting a first memory request priority register in a first processing element of a plurality of processing elements in a memory device of the memory system to a first priority value based at least in part on a first load-to-use distance hint from a compiler and a first instruction execution rate associated with a first processing element;
setting a second memory request priority register in a second processing element of the plurality of processing elements to a second priority value based at least in part on a second load-to-use distance hint from the compiler and a second instruction execution rate associated with a second processing element;
sending a first memory access request comprising the first priority value from the first processing element to a crossbar interconnect in the memory device, the memory device further comprising: a plurality of memory controllers, each of the plurality of processing elements and each of the plurality of memory controllers being coupled to the crossbar interconnect, the plurality of memory controllers comprising a memory controller that comprises a queue that buffers a plurality of memory access requests to a vault of stacked memory chips that are within the memory device, the plurality of memory access requests buffered in the queue comprising a second memory access request comprising the second priority value;
routing the first memory access request through the crossbar interconnect to the memory controller;
receiving the first memory access request at the memory controller;
determining that the first priority value is greater than the second priority value, wherein the first prior

Assignees

• IBM

Inventors

• Fleischer Bruce M
• Fox Thomas W
• Jacobson Hans M
• Nair Ravi

Classifications

• G06F13/18 Primary

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F13/1626

  by reordering requests · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title