Resistance change memory, method of manufacturing resistance change memory, and FET

Patent metadata

Field	Value
Publication number	US-9825096-B2
Application number	US-201514747215-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Sep 17, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.

First claim

What is claimed is:

1. A resistance change memory comprising:
a substrate having a surface
a first conductive line provided above the surface of the substrate;
a second conductive line provided above the first conductive line, and extending in a first direction along the surface of the substrate;
a third conductive line provided above the surface of the substrate and extending in a second direction, the second direction intersecting the first direction and the surface of the substrate;
a select transistor provided between the first and third conductive lines; and
a resistance change layer provided between the second and third conductive lines,
wherein the select transistor includes:
a first conductive layer provided on the first conductive line;
a first semiconductor layer as a channel including crystal grains, the first semiconductor layer being provided on the first conductive layer;
a second conductive layer provided on the first semiconductor layer, and connected to the third conductive line; and
a fourth conductive line as a gate extending in the first direction, the fourth conductive line facing to the first semiconductor layer,
wherein the first conductive layer and the first semiconductor layer include a predetermined impurity with a first impurity concentration and the second conductive layer includes no predetermined impurity or the predetermined impurity with a second impurity concentration less than the first impurity concentration, and
wherein the crystal grains in the first semiconductor layer include first crystal grains and second crystal grains in a first plane extending in a direction along the surface of the substrate, a crystal orientation of the first crystal grains in the first plane is {001}-plane, a crystal orientation of the second crystal grains in the first plane is {101}-plane, and a number of the first crystal grains is larger than a number of the second crystal grains.

2. The memory of claim 1 , wherein a number of crystal grains in which a crystal orientation in a parallel plane parallel to the first direction is {001}-plane, among the crystal grains in the first semiconductor layer, is larger than a number of crystal grains in which a crystal orientation in the parallel plane is {101}-plane.

3. The memory of claim 1 , wherein the predetermined impurity is at least one of Ge, Ar, F, and C.

4. The memory of claim 1 , wherein the first semiconductor layer has a compression stress in the first direction, and has a tensile stress in the second direction.

5. The memory of claim 1 , wherein the first and second conductive layers are second and third semiconductor layers each including crystal grains respectively, the first semiconductor layer includes a first conductive type impurity, and the second and third semiconductor layers include a second conductive type impurity.

6. The memory of claim 1 , further comprising a fifth conductive line stacked above the second conductive line, and extending in the first direction,
wherein the resistance change layer is further provided between the third and fifth conductive lines.

7. The memory of claim 1 , wherein a top end of the third conductive line is open.

8. The memory of claim 1 , further comprising a controller configured to change a resistance of the resistance change layer between the second and third conductive lines by flowing a current between the second and third conductive lines.

Assignees

• Toshiba Memory Corp

Inventors

• Ota Kensuke
• Saitoh Masumi

Classifications

• H01L27/2454 Primary

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L27/249

  Electricity · mapped topic

• H10B63/34 Primary

  of the vertical channel field-effect transistor type · CPC title