Semicondutor memory device and memory system including the same

Patent metadata

Field	Value
Publication number	US-9824755-B2
Application number	US-201414465995-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Nov 12, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a cell array including a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block;
a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and
a fuse circuit including a plurality of fuses, and configured to cut off an activation of word lines of the first defective block by blowing a fuse of the plurality of fuses.

2. The semiconductor memory device of claim 1 , wherein the first defective block includes a first set of memory cells electrically connected to a sub word line driver connected to a corresponding word line and a bit line sense amplifier connected to corresponding bit lines.

3. The semiconductor memory device of claim 2 , wherein the address information corresponds to a start address and an end address of rows of the first defective block.

4. The semiconductor memory device of claim 1 , wherein the fuse circuit is set to cut off an activation of all the word lines of the first defective block.

5. The semiconductor memory device of claim 1 , wherein the fuse circuit is configured to cut off an activation of a first set of word lines of the first defective block.

6. The semiconductor memory device of claim 5 , wherein a second word line included in the first defective block is remapped to become a redundant word line for repairing a defective word line of the cell array.

7. The semiconductor memory device of claim 6 , further comprising a redundant circuit to remap the second word line as the redundant word line.

8. The semiconductor memory device of claim 1 , wherein the fuse circuit is configured to cut off an activation of word lines included in a block adjacent to the first defective block.

9. The semiconductor memory device of claim 1 , further comprising a reorder decoder configured such that the first defective block is replaced with a second block of the cell array,
wherein the cell array includes a user area including the second block and a kernel area including the first defective block.

10. A memory system comprising:
a memory device comprising:
a memory cell array including a plurality of memory cells each connected to a word line, and divided into a first set of blocks, and a second set of blocks that includes at least a first defective block, each block including a plurality of word lines; and
a row decoder configured to inactivate a first set of word lines in the second set of blocks,
wherein the first and second sets of blocks correspond to row addresses; and

a host configured to receive address information of the second set of blocks, and access the memory device based on the address information,
wherein the memory device further includes:
a storage circuit configured to store address information of the second set of blocks, and to provide the address information to the host; and
a fuse circuit configured such that the row decoder inactivates the first set of word lines of the second set of blocks.

11. The memory system of claim 10 , wherein the memory device further includes a reorder decoder configured to replace a row address of the first defective block with a row address of the first set of blocks.

12. The memory system of claim 10 , wherein the memory device further includes a redundant circuit that replaces a defective word line of the first set of blocks with a first word line of the first defective block.

13. The memory system of claim 10 , wherein the second set of blocks includes a second block disposed adjacent to the first defective block, the second block having no defective cells.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sohn Young-Soo
• Park Chul-Woo
• Park Kwang-Il
• Yu Hak-Soo

Classifications

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C14/0018 Primary

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/702 Primary

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C11/40

  using transistors · CPC title