Optoelectronic device including improved thermal management

Patent metadata

Field	Value
Publication number	US-2016111618-A1
Application number	US-201514706141-A
Country	US
Kind code	A1
Filing date	May 7, 2015
Priority date	May 7, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A heterostructure for use in fabricating an optoelectronic device with improved thermal management is provided. The heterostructure can include a plurality of epitaxially grown layers including an n-type contact layer, an active layer, and a p-type contact layer. N-type and p-type electrodes for the n-type contact layer and p-type contact layer, respectively, can be embedded within an electrically insulating, thermally conductive semiconductor layer that is adjacent to the epitaxially grown layers. The electrically insulating, thermally conductive semiconductor layer can provide a larger lateral area for extracting heat generated by the active layer, so that there is improved thermal management within the device.

First claim

What is claimed is:

1 . A heterostructure comprising:
a plurality of epitaxially grown layers, including:
an n-type contact layer; and
a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer;
an n-type electrode to the n-type contact layer; a p-type electrode to the p-type contact layer; and an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of the thermal conductivity of at least one of the plurality of epitaxially grown layers.

2 . The heterostructure of claim 1 , wherein the p-type electrode and the n-type electrode are embedded within the electrically insulating, thermally conductive semiconductor layer.

3 . The heterostructure of claim 2 , wherein the electrically insulating, thermally conductive semiconductor layer is electrically conductive.

4 . The heterostructure of claim 3 , further comprising a set of insulating materials located between the p-type electrode and the electrically insulating, thermally conductive semiconductor layer and the n-type electrode and the electrically insulating, thermally conductive semiconductor layer.

5 . The heterostructure of claim 1 , further comprising an interface layer located between the p-type contact layer of the mesa region and the electrically insulating, thermally conductive semiconductor layer.

6 . The heterostructure of claim 1 , further comprising a set of thermally conductive fillers within the electrically insulating, thermally conductive semiconductor layer.

7 . The heterostructure of claim 1 , further comprising a submount for mounting the heterostructure to fabricate an optoelectronic device, wherein the optoelectronic device is located within a package.

8 . The heterostructure of claim 7 , wherein the package is placed within a cavity of a heat sink for extracting heat generated from the optoelectronic device.

9 . The heterostructure of claim 7 , wherein the electrically insulating, thermally conductive semiconductor layer is located between the heterostructure and the package.

10 . The heterostructure of claim 9 , wherein the electrically insulating, thermally conductive semiconductor layer includes a plurality of thermally conductive nanoparticles.

11 . An optoelectronic device, comprising:
a plurality of epitaxially grown layers, including:
a substrate;
an n-type contact layer to the substrate; and
a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer;
an n-type electrode to the n-type contact layer; a p-type electrode to the p-type contact layer; and an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of thermal conductivity of at least one of the plurality of epitaxially grown layers.

12 . The device of claim 11 , wherein the p-type electrode and the n-type electrode are embedded within the electrically insulating, thermally conductive semiconductor layer.

13 . The device of claim 12 , wherein the electrically insulating, thermally conductive semiconductor layer is electrically conductive.

14 . The device of claim 13 , further comprising a set of insulating materials located between the p-type electrode and the electrically insulating, thermally conductive semiconductor layer and the n-type electrode and the electrically insulating, thermally conductive semiconductor layer.

15 . The device of claim 11 , further comprising an interface layer located between the p-type contact layer of the mesa region and the electrically insulating, thermally conductive semiconductor layer.

16 . The device of claim 11 , further comprising a set of thermally conductive fillers within the electrically insulating, thermally conductive semiconductor layer.

17 . A method of fabricating a device, the method comprising:
epitaxially growing a plurality of layers on a substrate, wherein the plurality of layers includes:
a substrate;
an n-type contact layer to the substrate;
a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer; and
an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of the thermal conductivity of at least one of the plurality of epitaxially grown layer.

18 . The method of claim 17 , further comprising:
etching a first portion of the plurality of layers to expose the n-type contact layer; and forming an n-type electrode for contact to the n-type contact layer.

19 . The method of claim 18 , further comprising:
etching a second portion of the plurality of layers to expose the p-type contact layer; and forming a p-type electrode for contact to the p-type contact layer.

20 . The method of claim 19 , further comprising epitaxially growing the plurality of layers includes epitaxially growing an interface layer between the mesa region and the electrically insulating, thermally conductive semiconductor layer.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Shur Michael
• Shatalov Maxim S
• Dobrinsky Alexander
• Gaska Remigijus

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10H20/81

  Bodies · CPC title

• H10H20/01

  Manufacture or treatment · CPC title

• H10H20/8581 Primary

  characterised by their material · CPC title

• H01L33/005

  Electricity · mapped topic