Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof

Patent metadata

Field	Value
Publication number	US-9818801-B1
Application number	US-201615293971-A
Country	US
Kind code	B1
Filing date	Oct 14, 2016
Priority date	Oct 14, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A three-dimensional resistive memory device includes an alternating stack of electrically conductive layers and insulating layers. Resistive memory elements are provided between the electrically conductive layers and a semiconductor local bit line. The semiconductor local bit line includes a heterostructure of an inner semiconductor material layer having an inner-material band gap and an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band. A gate dielectric is located between a gate electrode and the inner semiconductor material layer.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers, wherein each layer in the alternating stack laterally extends along a first horizontal direction;
semiconductor local bit lines vertically extending through the alternating stack, contacting sidewalls of the insulating layers within the alternating stack, laterally surrounding a respective set of a gate dielectric and a gate electrode; and
resistive memory elements located between the electrically conductive layers and the semiconductor local bit lines,
wherein each of the semiconductor local bit lines comprises:
an inner semiconductor material layer having an inner-material band gap and laterally surrounding a respective gate dielectric; and
an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band gap.

2. The three-dimensional memory device of claim 1 , further comprising a plurality of selector elements located at each level of the electrically conductive layers and contacting a respective resistive memory element.

3. The three-dimensional memory device of claim 2 , wherein:
a combination of a resistive memory element among the resistive memory elements and a selector element among the plurality of selector elements is located at each level of the electrically conductive layers;
one of the resistive memory element and the selector element in the combination contacts a respective electrically conductive layer; and
another of the resistive memory element and the selector element in the combination contacts a respective outer semiconductor material layer.

4. The three-dimensional memory device of claim 3 , wherein each selector element comprises a combination of a discrete barrier material portion and a discrete conductive material portion located at a level of a respective electrically conductive layer and adjacent to a respective one of the semiconductor local bit lines.

5. The three-dimensional memory device of claim 3 , wherein each selector element comprises a diode.

6. The three-dimensional memory device of claim 1 , wherein each gate dielectric contacts a respective inner semiconductor material layer continuously from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack.

7. The three-dimensional memory device of claim 1 , further comprising a plurality of selector elements located at each level of the electrically conductive layers and contacting a respective resistive memory element and one element selected from the electrically conductive layers and the semiconductor local bit lines,
wherein the resistive memory elements comprise portions of resistive memory material layers located at each level of the electrically conductive layers, wherein each of the resistive memory material layers continuously extends from a bottommost layer within the alternating stack to a topmost layer within the alternating stack and laterally surrounds a respective one of the semiconductor local bit lines.

8. The three-dimensional memory device of claim 1 , wherein:
the outer semiconductor material layer laterally surrounds the inner semiconductor material layer;
a two-dimensional electron gas for electrical current conduction is present at, or in proximity to, an interface between the inner semiconductor material layer and the outer semiconductor material layer;
each of the semiconductor local bit lines has a conduction band having a minimum at, or in proximity to, the interface to form a quantum well;
a two-dimensional heterojunction between two different semiconductor materials is present at the interface; and
the two-dimensional heterojunction vertically extends with a substantially uniform horizontal cross-sectional shape.

9. The three-dimensional memory device of claim 1 , wherein:
the inner semiconductor material layer comprises an inner III-V compound semiconductor material; and
the outer semiconductor material layer comprises an outer III-V compound semiconductor material different from the inner III-V compound semiconductor material.

10. The monolithic three-dimensional memory device of claim 9 , wherein the inner and outer semiconductor material layers are selected from one of the following:
(a) the inner III-V compound semiconductor material is undoped, and the outer III-V compound semiconductor material is undoped; or
(b) an inner portion of the inner III-V compound semiconductor material is n-doped, an outer portion of the inner III-V compound semiconductor material is undoped, and the outer III-V compound semiconductor material is undoped; or
(c) an inner portion of the inner III-V compound semiconductor material is undoped, an outer portion of the inner III-V compound semiconductor material is n-type doped, and the outer III-V compound semiconductor material is undoped; or
(d) an inner portion of the inner III-V compound semiconductor material is undoped, an intermediate portion of the inner III-V compound semiconductor material is n-type doped, an outer portion of the inner III-V compound semiconductor material is undoped, and the outer III-V compound semiconductor material is undoped.

11. The monolithic three-dimensional memory device of claim 9 , wherein:
the inner III-V compound semiconductor material comprises a material selected from AlGaAs, GaAs, InAlAs, and InGaAlAs; and
the outer III-V compound semiconductor material comprises a material selected from GaAs, InGaAs, InP, InAs, and InGaAsP.

12. The three-dimensional memory device of claim 1 , wherein the resistive memory elements comprise at least one resistive memory material selected from a filament-forming dielectric material providing a reduced resistivity upon formation of conductive filaments therein and barrier modulated cell material in which vacancy concentration is modulated in a metal oxide material providing an increased resistivity upon reduction of oxygen vacancy therein.

13. The three-dimensional memory device of claim 1 , further comprising:
global bit lines laterally extending along a second horizontal direction that is different from the first horizontal direction, overlying or underlying the semiconductor local bit lines, and electrically shorted to a respective subset of the semiconductor local bit lines; and
separator dielectric material portions laterally extending along the second horizontal direction and located between each neighboring pair of global bit lines.

Assignees

• Sandisk Technologies Llc

Inventors

• Rabkin Peter
• Ratnam Perumal
• Petti Christopher J
• Higashitani Masaaki

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D30/471

  High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L29/122

  Electricity · mapped topic